Abstract: A game board device is provided for carrying and identifying game pieces that are divided into different piece types. The game board device includes a board, a plurality of optically identifying modules, and a processing module electrically coupled to the optically identifying modules. The optically identifying modules respectively correspond in position to detection regions of the board. Each of the optically identifying modules includes a light emitter that can emit light toward the corresponding detection region and a light receiver that can receive light reflected by the corresponding detection region. When any one of the detection regions is in an unoccupied mode, the corresponding optically identifying module can emit an unoccupied signal. When any one of the detection regions is in an occupied mode, the corresponding optically identifying module enables an identification signal that corresponds to the piece type of the corresponding game piece to be emitted therefrom.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a first transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. The first transistor is formed by a plurality of second transistors. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of each second transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of each second transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.

Abstract: A power supply circuit and a power distribution method thereof are provided. The power supply circuit includes a power input switch block, a power supply measurement block, a power supply conversion block and a power supply control block. The power input switch block provides a first power supply voltage to a load circuit based on an external power supply voltage from an adapter. The power supply measurement block measures a current of the first power supply voltage. The power supply conversion block is coupled to the battery module to provide a second power supply voltage to the load circuit. When a battery temperature of the battery module is higher than a critical temperature and a battery power of the battery module is higher than or equal to a critical power, the power supply control block limits the second power supply voltage provided to the load circuit.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.