Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate is provided, and a gate oxide layer, a gate structure, and a spacer structure are formed on the semiconductor substrate. The gate oxide layer is located between the gate structure and the semiconductor substrate in a vertical direction, and the spacer structure is located on a sidewall of the gate structure. A SiCoNi process is performed, and a ratio of nitrogen trifluoride (NF3) to ammonia (NH3) used in the SiCoNi process is greater than or equal to 0.35 and less than or equal to 0.4. A nickel silicide layer is formed in the semiconductor substrate after the SiCoNi process, and a part of the nickel silicide layer is located under the spacer structure in the vertical direction.

Abstract: A narrow bandpass filtering element includes a substrate, a bandpass filtering structure and an anti-reflection structure, and the bandpass filtering structure and anti-reflection structure are formed on two opposite surfaces of the substrate respectively. The bandpass filtering structure includes NbTiOx layers, first material layers with a higher refractive index than the NbTiOx layer, and second material layers with a lower refractive index than the NbTiOx layer, and the NbTiOx layers, first material layers and second material layers are stacked along a normal line of the substrate. Therefore, light in a specific wave band fitting a narrow passband can pass through the narrow bandpass filtering element.

Abstract: A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

Abstract: The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

Abstract: The present disclosure relates to medical implant components comprising a biocompatible-bioactive composite material layer (BACL), methods of making the medical implant components and applications of the medical implant components.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the barrier layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: A network management device (100) is disclosed, which includes a transceiver circuit (110), a memory (120), and a processor (130). The processor (130) executes following steps: detecting multiple second packet processing rules respectively corresponding to each of multiple packet sets; respectively for each of the multiple packet sets, updating a packet processing rule table (121) by utilizing the second packet processing rules being different from multiple first packet processing rules, and calculating an average rule quantity of the second packet processing rules being different from the multiple first packet processing rules; and determining whether to stop updating the packet processing rule table (121) based on the multiple average rule quantities.

Abstract: In order to maintain the white balance ratio of the mixed white light, a pixel unit is provided, which is composed of four sub-pixels of red, green, blue, and another green colors, and these sub-pixels are composed of a red LED element, a first green LED element, a blue LED element and a second green LED element. A control element is used to control the four sub-pixels of red, first green, blue and second green correspondingly by outputting control signals through the control channels. Base on the adjustment of the current, the brightness ratio of the above three colors is still maintained at the ratio of 3:6:1 of the white balance, and the ratio of the white balance of the white light after being mixed is also maintained.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: An impedance calibration circuit includes a variable impedance circuit, a detection circuit and a control circuit. The variable impedance circuit includes conduction paths connected in parallel between an output terminal and a supply terminal coupled to a first supply voltage. The variable impedance circuit is configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code. The detection circuit is configured to detect a change in impedance of the conduction paths by applying a second supply voltage to a reference terminal through a detection path, and accordingly generate an input voltage at the reference terminal. An electric potential of the second supply voltage is equal to an electric potential of the first supply voltage. The control circuit is configured to compare the input voltage with reference voltages to generate the calibration code.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Abstract: An organic light-emitting diode display device includes a first light-emitting layer, a first anode, a first reflective pattern, and a dielectric material. The first light-emitting layer, the first anode, and the first reflective pattern are located in a first sub-pixel region. The first anode is disposed under the first light-emitting layer in a vertical direction, and the first reflective pattern is disposed under the first anode in the vertical direction. The dielectric material is partly disposed between the first anode and the first reflective pattern, and the first reflective pattern is electrically connected with the first anode.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

Abstract: An impedance calibration circuit includes a variable impedance circuit, a detection circuit and a control circuit. The variable impedance circuit includes conduction paths connected in parallel between an output terminal and a supply terminal coupled to a first supply voltage. The variable impedance circuit is configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code. The detection circuit is configured to detect a change in impedance of the conduction paths by applying a second supply voltage to a reference terminal through a detection path, and accordingly generate an input voltage at the reference terminal. An electric potential of the second supply voltage is equal to an electric potential of the first supply voltage. The control circuit is configured to compare the input voltage with reference voltages to generate the calibration code.

Abstract: A voltage selector device includes a control circuit and a selection circuit. The control circuit is configured to adjust a level of a control node according to a power enable signal, a first supply voltage, and a second supply voltage. When the first supply voltage is powered up and the second supply voltage is not powered up, the control circuit adjusts the level of the control node to a first level, and when the second supply voltage is powered up, the control circuit adjusts the level of the control node to a second level that is different from the first level. The selection circuit is configured to output, based on the level of the control node and second supply voltage, a selected one of the first supply voltage and the second supply voltage that has a higher voltage level as an output voltage.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: A method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. The dielectric structure divides the metal gate into two sections.