Patents by Inventor Yen-Yi Lin

Yen-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250074444
    Abstract: A method for early warning a blind area of a vehicle. In the method, the electronic device obtains at least one target image acquired by at least one camera of the vehicle. The electronic device further determines parameters of at least one target object in each of the at least one target image and a three-dimensional detection frame for each of the at least one target object based on the parameters. The electronic device further obtains a target detection frame of each of the at least one target object in a top view image of a plane where the vehicle is located by projecting the three-dimensional detection frame into the top view image and outputs alert information in response that an overlapped area exists between the target detection frame and a preset blind area of the top view image.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 6, 2025
    Inventors: CHENG-FENG WANG, PO-CHUNG WANG, LI-CHE LIN, YEN-YI LIN
  • Patent number: 12154355
    Abstract: This application provides an image defect detection method. The method includes obtaining a first image and a second image of a flawless image. A third image is obtained from the second image and the first image, and a fourth image is obtained according to the second image and an image to be detected. A fifth image is obtained based on the third image and the second image. A sixth image is obtained based on the third image and the fourth image. A seventh image is obtained from the fifth image and the sixth image. A defect value of the fourth image is obtained according to the third image and the seventh image. A detection result of the fourth image is determined based on the defect value.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: November 26, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yen-Yi Lin, Hui-Xian Yang
  • Publication number: 20240142935
    Abstract: A method for detecting workpiece based on homogeneous multi-core architecture is illustrate. The method comprises: obtaining detecting images of detecting workpieces; identifying detecting areas of the detecting workpieces in the detecting images; dividing the preset rotation angle to obtain the rotation accuracy and initial rotation angles; based on each of the initial rotation angles, rotating the detecting areas to obtain a rotation area of each of the initial rotation angles; calculating similarity values between each of the rotation areas and a preset qualified area, and determining a largest similarity value as the target similarity value; and when the rotation accuracy is greater than or equal to a preset accuracy, identifying whether the detecting workpiece is a qualified workpiece according to the target similarity value and a preset similarity threshold.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 2, 2024
    Inventors: CHENG-FENG WANG, LI-CHE LIN, YEN-YI LIN
  • Publication number: 20240029423
    Abstract: A method for detecting defect in image is provided. The method obtains a number of original images, determines a first reference image from the original images, and performs a histogram matching on the original images excluding the first reference image according to the first reference image, to obtain a plurality of matched images. The method further generates a synthesized image according to pixel intensities of the matched images and pixel intensities of the first reference image; and uses the synthesized image as a second reference image to perform an image comparison with a test image, to generate a result of defect detection. A related device and a related non-transitory storage medium are also provided.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 25, 2024
    Inventors: LI-CHE LIN, YEN-YI LIN, CHENG-FENG WANG
  • Publication number: 20230316497
    Abstract: A method for detecting apparent defects in images of products acquires an original image of the product. Defects apparent in the original image are automatically detected by an automatic optical detection apparatus. When the original image comprises at least one apparent defect, the original image is cut into at least one partial image centered on the at least one apparent defect. Each partial image contains one defect. By determining whether the at least one partial image indicates a real defect or a false or ghost defect, a result of desired image (for further analysis), or undesired image (for discarding) is output. The original image is deemed a desired image or an undesired image based on the result. A defect detection system applying the method is also disclosed.
    Type: Application
    Filed: May 18, 2022
    Publication date: October 5, 2023
    Inventors: CHENG-FENG WANG, YING-TIEN HUANG, YEN-YI LIN
  • Publication number: 20230093969
    Abstract: This application provides a method of detecting printing defects. The method includes obtaining a first image of each character in a reference image. A third image of each character is obtained based on the first image of each character, a fourth image of each character is obtained based on a second image of each character obtained from an image to be detected. Once a fifth image of each character is obtained based on the third image of each character, a sixth image of each character is obtained according to the fourth image and the fifth image of each character, a detection result of each character in the image to be detected is determined according to the fifth image and the sixth image of the each character.
    Type: Application
    Filed: June 30, 2022
    Publication date: March 30, 2023
    Inventors: YEN-YI LIN, CHENG-FENG WANG, LI-CHE LIN
  • Publication number: 20230086131
    Abstract: This application provides an image defect detection method. The method includes obtaining a first image and a second image of a flawless image. A third image is obtained from the second image and the first image, and a fourth image is obtained according to the second image and an image to be detected. A fifth image is obtained based on the third image and the second image. A sixth image is obtained based on the third image and the fourth image. A seventh image is obtained from the fifth image and the sixth image. A defect value of the fourth image is obtained according to the third image and the seventh image. A detection result of the fourth image is determined based on the defect value.
    Type: Application
    Filed: June 23, 2022
    Publication date: March 23, 2023
    Inventors: YEN-YI LIN, HUI-XIAN YANG
  • Publication number: 20170310724
    Abstract: A method for processing media data includes determining at least one target feature and determining corresponding effect relating to the at least one target feature. Media data is received from a sender. Once the at least one target feature is detected in the media data, the corresponding effect relating to the at least one target feature is applied to the media data.
    Type: Application
    Filed: March 27, 2017
    Publication date: October 26, 2017
    Inventors: SHU-LUN CHANG, YEN-YI LIN
  • Publication number: 20150206985
    Abstract: TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions.
    Type: Application
    Filed: March 30, 2015
    Publication date: July 23, 2015
    Applicant: DIODES INCORPORATED
    Inventors: John Earnshaw, Wolfgang Kemper, Yen-Yi Lin, Steve Badcock, Mark French
  • Patent number: 9048106
    Abstract: TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 2, 2015
    Assignee: Diodes Incorporated
    Inventors: John Earnshaw, Wofgang Kemper, Yen-Yi Lin, Steve Badcock, Mark French
  • Publication number: 20140167204
    Abstract: TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: DIODES INCORPORATED
    Inventors: John Earnshaw, Wofgang Kemper, Yen-Yi Lin, Steve Badcock, Mark French
  • Publication number: 20110266624
    Abstract: An ESD protection device for an I/O pad (401); the device comprising a MOS transistor (420) having at least one elongated source region (422) and at least one elongated drain region (421) in a substrate (400) of first conductivity, the length (420a) of the source and drain regions oriented in a direction, the source tied to ground potential (430); a diode having an area including at least one elongated anode region and at least one elongated cathode region in a well of opposite conductivity, the lengths of the anode and cathode regions oriented in the same direction as the transistor regions; the diode area and the well divided normal to the lengths of the anode and cathode regions into two portions (anode portions 411x, 411y, cathode portions 412x, 412y, length portions 410x, 410y, well portions 440x, 440y); and the anode portions connected to the I/O pad, and the cathode portions connected to the transistor drain.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charvaka DUVVURY, Yen-Yi LIN
  • Patent number: 6232157
    Abstract: The specification describes thin film transistor integrated circuits wherein the TFT devices are field effect transistors with inverted structures. The interconnect levels are produced prior to the formation of the transistors. This structure leads to added flexibility in processing. The inverted structure is a result of removing the constraints in traditional semiconductor field effect device manufacture that are imposed by the necessity of starting the device fabrication with the single crystal semiconductor active material. In the inverted structure the active material, preferably an organic semiconductor, is formed last in the fabrication sequence. In a preferred embodiment the inverted TFT devices are formed on a flexible printed circuit substrate.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: May 15, 2001
    Assignee: Agere Systems Inc.
    Inventors: Ananth Dodabalapur, Yen-Yi Lin, Venkataram Reddy Raju
  • Patent number: 6040238
    Abstract: A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by thermal annealing is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. The semiconductor substrate is annealed by rapid thermal annealing (RTA). Thereafter, an oxide layer is deposited overlying the silicide layer. Because the silicide layer has been annealed, silicon atoms are prevented from diffusing into the silicide layer and forming voids in the polysilicon layer. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: March 21, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chie-Ming Yang, Jih-Hwa Wang, Yen-Yi Lin