Patents by Inventor Yen-Yi Wu
Yen-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088070Abstract: Provided is a package structure and a method of forming the same. The package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. The semiconductor package includes a die. The stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. The plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yi Hsu, Kai-Chiang Wu, Yen-Ping Wang
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Patent number: 10713410Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.Type: GrantFiled: April 25, 2019Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chao-Hung Wang, Yen-Yi Wu, Shih-Chun Chen, Yao-Wen Chang, Meng-Kai Hsu
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Publication number: 20190251224Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Inventors: Chao-Hung WANG, Yen-Yi WU, Shih-Chun CHEN, Yao-Wen CHANG, Meng-Kai HSU
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Patent number: 10275559Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.Type: GrantFiled: November 18, 2016Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hung Wang, Yen-Yi Wu, Shih-Chun Chen, Yao-Wen Chang, Meng-Kai Hsu
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Publication number: 20180144083Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.Type: ApplicationFiled: November 18, 2016Publication date: May 24, 2018Inventors: Chao-Hung WANG, Yen-Yi WU, Shih-Chun CHEN, Yao-Wen CHANG, Meng-Kai HSU
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Publication number: 20140312496Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.Type: ApplicationFiled: April 30, 2014Publication date: October 23, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yen-Yi WU, Wei-Yueh SUNG, Pao-Huei CHANG CHIEN, Chi-Chih CHU, Cheng-Yin LEE, Gwo-Liang WENG
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Patent number: 7642133Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.Type: GrantFiled: July 26, 2007Date of Patent: January 5, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yen-Yi Wu, Wei-Yueh Sung, Pao-Huei Chang Chien, Chi-Chih Chu, Cheng-Yin Lee, Gwo-Liang Weng
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Patent number: 7635917Abstract: The present invention relates to a three-dimensional package and method of making the same. The package includes a first substrate, a first chip, a second substrate, a second chip, a spacer, and a first molding compound. The first chip is electrically connected to the first substrate. The second substrate is electrically connected to the first substrate. The second chip is electrically connected to the second substrate. One end of the spacer is attached to the first chip, and the other end of the spacer is attached to the second chip. The first molding compound encapsulates the first substrate, the first chip, the second substrate, the second chip, and the spacer. In the present invention, the adhesion between the spacer and the second chip is enhanced, and the overall thickness of the three-dimensional package is reduced.Type: GrantFiled: October 30, 2007Date of Patent: December 22, 2009Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ching-Chun Wang, Yen-Yi Wu, Sem-Wei Lin
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Publication number: 20080164595Abstract: The present invention relates to a stackable semiconductor package and the method for making the same. The stackable semiconductor package comprises a first substrate, a semiconductor device, a plurality of stud bumps, a plurality of first wires, a second substrate, and a molding compound. The semiconductor device is disposed on the first substrate and electrically connected to the first substrate. The stud bumps are above the semiconductor device. The first wires are used for electrically connecting the stud bumps and the first substrate. The stud bumps are in contact with the second substrate. The molding compound encapsulates the first substrate, the semiconductor device, the stud bumps, the first wires, and the second substrate, and thus, the second substrate will not undergo wire bonding, and will not be suspended and shake or sway, as present in a conventional stackable semiconductor package.Type: ApplicationFiled: January 3, 2008Publication date: July 10, 2008Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yen-Yi Wu, Pao-Huei Chang Chien, Wei-Yueh Sung
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Publication number: 20080142957Abstract: The present invention relates to a three-dimensional package and method of making the same. The package includes a first substrate, a first chip, a second substrate, a second chip, a spacer, and a first molding compound. The first chip is electrically connected to the first substrate. The second substrate is electrically connected to the first substrate. The second chip is electrically connected to the second substrate. One end of the spacer is attached to the first chip, and the other end of the spacer is attached to the second chip. The first molding compound encapsulates the first substrate, the first chip, the second substrate, the second chip, and the spacer. In the present invention, the adhesion between the spacer and the second chip is enhanced, and the overall thickness of the three-dimensional package is reduced.Type: ApplicationFiled: October 30, 2007Publication date: June 19, 2008Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ching-Chun Wang, Yen-Yi Wu, Sem-Wei Lin
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Publication number: 20080073769Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.Type: ApplicationFiled: July 26, 2007Publication date: March 27, 2008Inventors: Yen-Yi Wu, Wei-Yueh Sung, Pao-Huei Chang Chien, Chi-Chih Chu, Cheng-Yin Lee, Gwo-Liang Weng
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Publication number: 20080076208Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.Type: ApplicationFiled: July 26, 2007Publication date: March 27, 2008Inventors: Yen-Yi Wu, Wei-Yueh Sung, Pao-Huei Chang Chien, Chi-Chih Chu, Cheng-Yin Lee, Gwo-Liang Weng