Abstract: The application discloses a time-of-flight generating circuit, coupled to a first transducer and a second transducer, wherein there is a distance greater than zero between the first transducer and the second transducer, and a fluid having a flow speed flows sequentially through the first transducer and the second transducer, wherein the time-of-flight generating circuit includes: a transmitter, coupled to the first transducer; a receiver, coupled to the second transducer; a signal processing circuit, coupled to the transmitter and the receiver; and a correlation circuit, a measuring circuit and a transformation circuit, coupled to the signal processing circuit. The application also discloses a chip, flow meter, and method of the same.

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer have a distance greater than zero, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer, the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: The application discloses a time-to-digital conversion circuit (100) including a first oscillator (110), a second oscillator (120), a first counting circuit (130), a second counting circuit (140), a first conversion circuit (150) and a processing circuit (160). The first oscillator is activated by a first signal and includes oscillating units having a first delay amount, wherein the first counting circuit is configured to count a number of times that the first tail end output signal of the first oscillator changes and store the same as a first counting result; the second counting circuit counts a number of oscillating units with an output change, other than the first tail end oscillating unit and stores the same as a second counting result; the first conversion circuit generates a first conversion signal according to the first counting result and the second counting result; the processing circuit generates the output signal at least according to the first conversion signal.

Abstract: A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.

Abstract: The application discloses a time-of-flight generating circuit, coupled to a first transducer and a second transducer, wherein there is a distance greater than zero between the first transducer and the second transducer, and a fluid having a flow speed flows sequentially through the first transducer and the second transducer, wherein the time-of-flight generating circuit includes: a transmitter, coupled to the first transducer; a receiver, coupled to the second transducer; a signal processing circuit, coupled to the transmitter and the receiver; and a correlation circuit, a measuring circuit and a transformation circuit, coupled to the signal processing circuit. The application also discloses a chip, flow meter, and method of the same.

Abstract: The application discloses a time-of-flight (TOF) generating circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer are arranged in a pipeline (120) filled with fluid. The TOF generating circuit includes a first transmitter (106) and a first receiver (108), a second transmitter (110) and a second receiver (112), a signal generating circuit (114), a correlation circuit (116), and a processing circuit (118). Under different ambient factors, the signal generating circuit generates, respectively, a first signal and a second signal, which are received by the second receiver and the first receiver to generate a first receiving signal (RS1) and a second receiving signal (RS2), respectively. The correlation circuit performs a correlation operation to generate a first correlation signal (CS1). The processing circuit generates the TOF variation according at least to the first correlation signal (118).

Abstract: The application discloses a time-to-digital conversion circuit (100) including a first oscillator (110), a second oscillator (120), a first counting circuit (130), a second counting circuit (140), a first conversion circuit (150) and a processing circuit (160). The first oscillator is activated by a first signal and includes oscillating units having a first delay amount, wherein the first counting circuit is configured to count a number of times that the first tail end output signal of the first oscillator changes and store the same as a first counting result; the second counting circuit counts a number of oscillating units with an output change, other than the first tail end oscillating unit and stores the same as a second counting result; the first conversion circuit generates a first conversion signal according to the first counting result and the second counting result; the processing circuit generates the output signal at least according to the first conversion signal.

Abstract: The present application discloses a signal processing circuit (100), coupled to a first transducer (102) and a second transducer (104), wherein the first transducer and the second transducer have a distance greater than zero, and a fluid having a flow velocity flows sequentially through the first transducer and the second transducer, the signal processing circuit includes: a first transmitter (106), coupled to the first transducer; a first receiver (108), coupled to the first transducer; a second transmitter (110), coupled to the second transducer; a second receiver (112), coupled to the second transducer; and a control unit (114), coupled to the first transmitter, the first receiver, the second transmitter and the second receiver. The present application further provides a related chip, a flow meter and a method.

Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.

Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.

Abstract: A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.

Abstract: The present application provides an advertising system, which includes a signage device, wherein the signage device includes a display panel configured to play a video; a camera module configured to capture an image; a determining module configured to determine whether or not a human face exists in the image; a wireless transmission module, wherein the wireless transmission module transmits a connection information when the determining module determines that there is a human face in the image; a first communication module; and an user device, wherein the user device includes a wireless reception module; a second communication module; wherein the second communication module establishes a wireless connection with the first communication module according to the connection information when the wireless reception module receives the connection information, and the signage device transmits an audio signal to the user device via the wireless connection.

Abstract: A frequency-modulated carrier receiver includes a signal extractor and an injection-locked oscillator. The signal extractor is configured to operably receive a frequency-modulated carrier and generate an injection signal based on the frequency-modulated carrier, so that the injection signal has a relatively smaller frequency variation than the frequency-modulated carrier. The injection-locked oscillator is coupled with the signal extractor and configured to operably filter out noise components in the injection signal to generate an output signal.

Abstract: A process, voltage, and temperature compensated oscillator, formed on an integrate circuit implemented by a semiconductor process, receives a supply voltage and includes: a variation bias unit provided with a variation bias output terminal and generating a process, voltage, and temperature compensated signal; a controlled oscillating unit provided with a control input terminal and an oscillating output and determining a signal oscillating frequency at the oscillating output terminal according to a signal at the control input terminal; and a tuning unit provided with a tuning input terminal, a compensating input terminal, a control output terminal, and a variable-parameter element, wherein the variable-parameter element includes a parameter and is coupled to the control output terminal, and the tuning unit determines the parameter according to a signal at the variation bias output terminal and a voltage signal or a digital signal received at the tuning input terminal.

Abstract: A phase/frequency detector module, applicable to a digital phase-locked loop, includes: an edge detector for receiving a reference clock signal and a counting clock signal, where when a positive edge of the counting clock signal occurs, if a positive edge of the reference clock signal has occurred, the edge detector outputs an edge-detected signal, else the edge detector outputs an edge-not-detected signal; a counter coupled to the edge detector, where if receiving the edge-detected signal, the counter outputs a counting result forming a frequency error signal, resets, and loads a count value, and if receiving the edge-not-detected signal, the counter continues to count on the positive edge of the counting clock signal; and a frequency phase converter for performing integration over the counting result, where the integral forms a phase error signal.

Abstract: Method and associated apparatus of data extraction, including: sampling a signal and obtaining a plurality of sampled values, providing a reference sample quantity when the sampled values transit, providing a unit bit sample quantity according to the reference sample quantity, and corresponding each of the sampled values to each data bit of the signal according to the unit bit sample quantity.

Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.

Abstract: Method and associated apparatus of data extraction, including: sampling a signal and obtaining a plurality of sampled values, providing a reference sample quantity when the sampled values transit, providing a unit bit sample quantity according to the reference sample quantity, and corresponding each of the sampled values to each data bit of the signal according to the unit bit sample quantity.

Abstract: A frequency locking method, for locking an output signal outputted from a frequency locking circuit to a target frequency, comprising: (a) detecting an output frequency of the output signal, wherein the output signal is generated according to an oscillating frequency of a controllable oscillator; (b) computing a frequency difference between the output frequency and the target frequency; (c) utilizing a controllable factor adjusting device to provide and to adjust a normalization factor according to the frequency difference, to anticipate a gain of the controllable oscillator and to provide a control signal related with the normalization factor and the frequency difference, wherein the output frequency is related with a product of the normalization factor and the gain of the controllable oscillator; and (d) controlling the controllable oscillator according to the control signal, such that the output frequency approaches to the target frequency.

Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.