Patents by Inventor Yen-Ying LIN

Yen-Ying LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250076369
    Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ronald Kuo-Hua Ho, Kun-Yu Wang, Yen-Chang Shih, Sung-Te Chen, Cheng-Han Wu, Yi-Ying Liao, Chun-Ming Huang, Yen-Feng Lu, Ching-Yu Tsai, Tai-Lai Tung, Kuan-Fu Lin, Bo-Kang Lai, Yao-Syuan Lee, Tsyr-Rou Lin, Ming-Chao Tsai, Li-Hsuan Chiu
  • Publication number: 20250063720
    Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yen-Chieh Huang, Wei-Gang Chiu, Kai-Wen Cheng, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12218173
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Publication number: 20250031388
    Abstract: A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 23, 2025
    Inventors: I-Che Lee, Pin-Ju Chen, Wei-Gang Chiu, Yen-Chieh Huang, Kai-Wen Cheng, Huai-Ying Huang, Yu-Ming Lin
  • Patent number: 10345371
    Abstract: A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: July 9, 2019
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Jyh-Chyurn Guo, Yen-Ying Lin
  • Publication number: 20170242065
    Abstract: A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.
    Type: Application
    Filed: November 15, 2016
    Publication date: August 24, 2017
    Inventors: Jyh-Chyurn GUO, Yen-Ying LIN