Abstract: A test cell structure of a display panel is disposed in the peripheral region of the display panel. First conductive lines and second conductive lines extend from the display region to the peripheral region, and the amounts of the first and second conductive lines are the same. The test cell structure includes a plurality of first test transistors, a plurality of second test transistors, and a plurality of first shorting bars. The drains of the first test transistors are electrically connected to the first conductive lines respectively, and their sources are electrically connected to the first shorting bars. The sources of the second test transistors are electrically connected to the drains of the first test transistors respectively, and their drains are electrically connected to the second conductive lines. The first test transistors are disposed between the second test transistors and the display region.

Abstract: A test cell structure of a display panel is disposed in the peripheral region of the display panel. First conductive lines and second conductive lines extend from the display region to the peripheral region, and the amounts of the first and second conductive lines are the same. The test cell structure includes a plurality of first test transistors, a plurality of second test transistors, and a plurality of first shorting bars. The drains of the first test transistors are electrically connected to the first conductive lines respectively, and their sources are electrically connected to the first shorting bars. The sources of the second test transistors are electrically connected to the drains of the first test transistors respectively, and their drains are electrically connected to the second conductive lines. The first test transistors are disposed between the second test transistors and the display region.