Patents by Inventor Yen-Yu SHIH
Yen-Yu SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134645Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P Singh, Ching-Yu Hung
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Patent number: 11957444Abstract: This specification describes systems and methods for using Zero Echo Time (ZTE) magnetic resonance imaging (MRI) sequences for applications to functional MRI (fMRI). In some examples, a system for functional magnetic resonance imaging includes a magnetic resonance imaging (MRI) scanner and a control console implemented on at least one processor. The control console is configured for executing, using the MRI scanner, a zero echo time (ZTE) pulse sequence; acquiring, using the MRI scanner, magnetic resonance data in response to the ZTE pulse sequence; and constructing at least one MRI image using the magnetic resonance data and measuring tissue oxygenation (PtO2)-related T1 changes as a proxy of neural activity changes of a subject using the at least one MRI image.Type: GrantFiled: August 8, 2022Date of Patent: April 16, 2024Assignee: THE UNIVERSITY OF NORTH CAROLINA AT CHAPEL HILLInventors: Yen-Yu Shih, Martin John MacKinnon, Yuncong Ma, Wei-Tang Chang
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Patent number: 11954496Abstract: In various examples, systems and methods for reducing written requirements in a system on chip (SoC) are described herein. For instance, a total number of iterations may be determined for processing data, such as data representing an array. In some circumstances, a set of iterations may include a first number of iterations that is less than a second number of iterations. As such, and during execution of the set of iterations, a predicate flag corresponding to an excess iteration of the set of iterations may be generated, where the excess iteration corresponds to an iteration that is part of a number of excess iterations that is associated with a difference between the first number of iterations and the second number of iterations. Based on the predicate flag, one or more first values corresponding to the iteration may be prevented from being written to memory.Type: GrantFiled: August 2, 2021Date of Patent: April 9, 2024Assignee: NVIDIA CorporationInventors: Ching-Yu Hung, Ravi P Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani
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Patent number: 11940947Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.Type: GrantFiled: January 6, 2023Date of Patent: March 26, 2024Assignee: NVIDIA CorporationInventors: Ching-Yu Hung, Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani
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Patent number: 11934829Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.Type: GrantFiled: December 9, 2022Date of Patent: March 19, 2024Assignee: NVIDIA CorporationInventors: Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P Singh, Ching-Yu Hung
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Publication number: 20230380187Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Harry-Hak-Lay CHUANG, Wen-Chun YOU, Hung Cho WANG, Yen-Yu SHIH
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Patent number: 11800724Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.Type: GrantFiled: December 27, 2021Date of Patent: October 24, 2023Inventors: Harry-Hak-Lay Chuang, Wen-Chun You, Hung Cho Wang, Yen-Yu Shih
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Publication number: 20230042314Abstract: This specification describes systems and methods for using Zero Echo Time (ZTE) magnetic resonance imaging (MRI) sequences for applications to functional MRI (fMRI). In some examples, a system for functional magnetic resonance imaging includes a magnetic resonance imaging (MRI) scanner and a control console implemented on at least one processor. The control console is configured for executing, using the MRI scanner, a zero echo time (ZTE) pulse sequence; acquiring, using the MRI scanner, magnetic resonance data in response to the ZTE pulse sequence; and constructing at least one MRI image using the magnetic resonance data and measuring tissue oxygenation (PtO2)-related T1 changes as a proxy of neural activity changes of a subject using the at least one MRI image.Type: ApplicationFiled: August 8, 2022Publication date: February 9, 2023Inventors: Yen-Yu Shih, Martin John MacKinnon, Yuncong Ma, Wei-Tang Chang
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Publication number: 20220123051Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.Type: ApplicationFiled: December 27, 2021Publication date: April 21, 2022Inventors: Harry-Hak-Lay CHUANG, Wen-Chun YOU, Hung Cho WANG, Yen-Yu SHIH
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Patent number: 11244983Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.Type: GrantFiled: June 4, 2020Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Wen-Chun You, Hung Cho Wang, Yen-Yu Shih
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Publication number: 20200411590Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.Type: ApplicationFiled: June 4, 2020Publication date: December 31, 2020Inventors: Harry-Hak-Lay CHUANG, Wen-Chun YOU, Hung Cho WANG, Yen-Yu SHIH