Abstract: A method for cutting off a fin in a field effect transistor, comprising: step 1: forming fins and first spacing regions, there are two types of fins—the first type is configured to be cut off and a second type is configured to be reserved; and forming a first material layer to fill the first spacing regions; step 2: forming a first pattern structure comprising first strip structures aligning to one first type fin and second spacing regions; step 3: forming second sidewalls on two sides of each first strip structure; step 4: removing the first strip structures to form a second pattern structure by the second sidewalls; step 5: etching away the first material layer and the first type of fins by using the second sidewalls as a mask ; step 6: removing the second sidewalls and the remaining first material layer. The present application enables using less advanced lithography equipment.

Abstract: The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.

Abstract: A method for cutting off a fin in a field effect transistor, comprising: step 1: forming fins and first spacing regions, there are two types of fins—the first type is configured to be cut off and a second type is configured to be reserved; and forming a first material layer to fill the first spacing regions; step 2: forming a first pattern structure comprising first strip structures aligning to one first type fin and second spacing regions; step 3: forming second sidewalls on two sides of each first strip structure; step 4: removing the first strip structures to form a second pattern structure by the second sidewalls; step 5: etching away the first material layer and the first type of fins by using the second sidewalls as a mask ; step 6: removing the second sidewalls and the remaining first material layer. The present application enables using less advanced lithography equipment.

Abstract: The disclosure provides a method for making a self-aligned double pattern, A silicon substrate with a first oxide layer, an amorphous silicon layer and an organic layer, etching the organic layer and the amorphous silicon layer, and covering them with a first silicon nitride layer; remove the first silicon nitride layer in the amorphous silicon pattern, forming first silicon nitride sidewall patterns on the amorphous silicon pattern's sidewalls; removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; defining the morphology of a fin field-effect transistor, form core patterns and covering them with a thin silicon nitride layer; depositing a second oxide layer; defining the fin field-effect transistor's height, and etching back the second oxide layer till the height of the core patterns satisfies the defined fin field-effect transistor height; removing the thin silicon nitride layer, depositing a third oxide layer to cover the core patterns.

Abstract: The disclosure provides a method for making a self-aligned double pattern, A silicon substrate with a first oxide layer, an amorphous silicon layer and an organic layer, etching the organic layer and the amorphous silicon layer, and covering them with a first silicon nitride layer; remove the first silicon nitride layer in the amorphous silicon pattern, forming first silicon nitride sidewall patterns on the amorphous silicon pattern's sidewalls; removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; defining the morphology of a fin field-effect transistor, form core patterns and covering them with a thin silicon nitride layer; depositing a second oxide layer; defining the fin field-effect transistor's height, and etching back the second oxide layer till the height of the core patterns satisfies the defined fin field-effect transistor height; removing the thin silicon nitride layer, depositing a third oxide layer to cover the core patterns.

Abstract: The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.