Abstract: An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

Abstract: Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

Abstract: An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

Abstract: An apparatus for detecting a source code error location in a mixed-mode program is disclosed. The apparatus may include a compiler, a mapping table generator, a simulator, a comparison data generator and an error location detector. The apparatus extracts low-level data while simulating a verification program and while simulating a reference program. The low-level data is mapped to mapping tables for a verification program and a reference program, and by comparing the tables it is determined if there is an error in the mixed-mode program and if so, where.

Abstract: An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information.

Abstract: A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.

Abstract: Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

Abstract: An apparatus for detecting a source code error location in a mixed-mode program is disclosed. The apparatus may include a compiler, a mapping table generator, a simulator, a comparison data generator and an error location detector. The apparatus extracts low-level data while simulating a verification program and while simulating a reference program. The low-level data is mapped to mapping tables for a verification program and a reference program, and by comparing the tables it is determined if there is an error in the mixed-mode program and if so, where.

Abstract: A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.

Abstract: An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information.