Patents by Inventor YenLung Li
YenLung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971826Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.Type: GrantFiled: December 21, 2021Date of Patent: April 30, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, A. Harihara Sravan, YenLung Li
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Patent number: 11971829Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.Type: GrantFiled: December 21, 2021Date of Patent: April 30, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, A. Harihara Sravan, YenLung Li
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Publication number: 20240071433Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, YenLung Li, Siddarth Naga Murty Bassa, Jeongduk Sohn
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Patent number: 11907545Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: GrantFiled: April 28, 2022Date of Patent: February 20, 2024Assignee: SanDisk Technologies LLCInventors: YenLung Li, Siddarth Naga Murty Bassa, Chen Chen, Hua-Ling Cynthia Hsu
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Publication number: 20240055051Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.Type: ApplicationFiled: August 15, 2022Publication date: February 15, 2024Applicant: SanDisk Technologies LLCInventors: Xiang Yang, YenLung Li, James Kai
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Patent number: 11901019Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: GrantFiled: February 8, 2022Date of Patent: February 13, 2024Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, Masaaki Higashitani, YenLung Li, Chen Chen
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Patent number: 11776589Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: GrantFiled: April 28, 2022Date of Patent: October 3, 2023Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, YenLung Li
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Patent number: 11755211Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.Type: GrantFiled: October 3, 2022Date of Patent: September 12, 2023Assignee: Western Digital Technologies, Inc.Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
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Patent number: 11735288Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.Type: GrantFiled: February 16, 2022Date of Patent: August 22, 2023Assignee: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, YenLung Li
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Publication number: 20230260589Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.Type: ApplicationFiled: February 16, 2022Publication date: August 17, 2023Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, YenLung Li
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Publication number: 20230095127Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: ApplicationFiled: April 28, 2022Publication date: March 30, 2023Applicant: SanDisk Technologies LLCInventors: YenLung Li, Siddarth Naga Murty Bassa, Chen Chen, Hua-Ling Cynthia Hsu
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Publication number: 20230085776Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: ApplicationFiled: May 12, 2022Publication date: March 23, 2023Applicant: SanDisk Technologies LLCInventors: Siddarth Naga Murty Bassa, YenLung Li, Hua-Ling Cynthia Hsu
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Publication number: 20230083903Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.Type: ApplicationFiled: December 21, 2021Publication date: March 16, 2023Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, A. Harihara Sravan, YenLung Li
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Publication number: 20230080999Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.Type: ApplicationFiled: December 21, 2021Publication date: March 16, 2023Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, A. Harihara Sravan, YenLung Li
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Publication number: 20230081623Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: ApplicationFiled: February 8, 2022Publication date: March 16, 2023Applicant: SANDISK TECHNOLOGIES LLCInventors: Hua-Ling Cynthia Hsu, Masaaki Higashitani, YenLung Li, Chen Chen
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Publication number: 20230085405Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.Type: ApplicationFiled: April 28, 2022Publication date: March 16, 2023Applicant: SanDisk Technologies LLCInventors: Hua-Ling Cynthia Hsu, YenLung Li
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Publication number: 20230022998Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
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Patent number: 11487446Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.Type: GrantFiled: February 12, 2021Date of Patent: November 1, 2022Assignee: Western Digital Technologies, Inc.Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
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Patent number: 11386961Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.Type: GrantFiled: December 20, 2019Date of Patent: July 12, 2022Assignee: SanDisk Technologies LLCInventors: YenLung Li, Chen Chen, Min Peng, Mitsuyuki Watanabe
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Patent number: 11380417Abstract: Aspects of a storage device are provided that reduce calculations for identifying physical locations of data during a read operation. In one aspect, a memory device includes one or more memory arrays. Each array includes multiple chunks of memory. The device includes a first set of registers for storing prefixed starting addresses for each array. The device further includes control logic that may identify bad physical address in each array. For each successive chunk in each array and based on the prefixed starting address and the bad physical address locations, the device may determine a pointer to a starting physical address for the chunk. The pointer may be stored in a second set of registers for use in register read operations.Type: GrantFiled: June 3, 2021Date of Patent: July 5, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Cynthia Hsu, YenLung Li, Min Peng