Abstract: The present invention relates to an electric resistance welder that includes a compressor, a welding holder, and a welding rod, wherein air compressed by the compressor may be introduced into the welding rod through the welding holder and is then discharged through air outlets formed in the welding rod.

Abstract: A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.

Abstract: A semiconductor device may include a semiconductor substrate having a first deep N well and/or a second deep N well, a first isolation layer over a first deep N well, and/or a first P well over a first deep N well. A semiconductor device may include an NMOS transistor over a first P well and/or a PMOS transistor over a first deep N well at an opposite side of a first isolation layer. A semiconductor device may include a second P well over a second deep N well, a second isolation layer interposed between a second deep N well and a second P well, and/or an emitter including first type impurities over a second deep N well. A semiconductor device may include a third isolation layer over a second P well, a collector including first type impurities over a second P well, and/or a base formed over a second P well and/or having a bottom surface to make contact with an emitter.

Abstract: A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.

Abstract: An equivalent circuit of an inductor is provided with a five wire structure. A first wire has a first resistor, an inductor, and a third resistor connected in series. A second wire is connected in parallel with the first wire and has a second resistor. A third wire is connected in parallel with the first and second wires and has a third capacitor. A fourth wire is serially connected to a first common node of the first, second, and third wires, and has a first capacitor connected between the first common node and a first sub capacitor and a first sub resistor connected in parallel. A fifth wire is serially connected to a second common node of the first, second, and third wires, and has a second capacitor connected between the second common node and a second sub capacitor and a second sub resistor connected in parallel.

Abstract: A semiconductor device and a method for manufacturing the same are provided. An n-well region can be formed on a semiconductor substrate, and a base contact region can be formed on the n-well region. An emitter contact region, a collector contact region, and a p-base region can also be formed on the n-well. The emitter and collector contact regions can include n-type ions, and the base contact region and the p-base region can include p-type ions. Thus, the semiconductor device can include an n-channel metal oxide semiconductor transistor and an NPN bipolar transistor.

Abstract: A Bi-CMOS semiconductor device and method for manufacturing the same are provided. An n-well can be formed in a semiconductor substrate, and an NMOS transistor can be provided on the substrate separated from the n-well by a device isolation layer. An NPN bipolar transistor can be formed using the n-well. In particular, a collector contact region and a p-base region can be provided in the n-well. In addition, a base contact region and an emitter contact region can be disposed in the p-base region. A silicide is provided on the source and drain regions and the gate of the NMOS transistor, and the base contact region of the NPN bipolar transistor.

Abstract: A trench transistor and a manufacturing method for the same are disclosed. The manufacturing method includes preparing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a gate oxide layer over an inner wall of the trench, forming a gate having a first conductivity type by embedding polysilicon in the trench, the gate including a protruding portion protruding over a surface of the semiconductor substrate, forming a barrier layer by implanting second conductivity type ions in the protruding portion, and forming a second conductivity type source region over the surface of the semiconductor substrate.

Abstract: An equivalent circuit of an inductor is provided with a five wire structure. A first wire has a first resistor, an inductor, and a third resistor connected in series. A second wire is connected in parallel with the first wire and has a second resistor. A third wire is connected in parallel with the first and second wires and has a third capacitor. A fourth wire is serially connected to a first common node of the first, second, and third wires, and has a first capacitor connected between the first common node and a first sub capacitor and a first sub resistor connected in parallel. A fifth wire is serially connected to a second common node of the first, second, and third wires, and has a second capacitor connected between the second common node and a second sub capacitor and a second sub resistor connected in parallel.

Abstract: A self-aligned bipolar semiconductor device and a fabrication method thereof are provided. After a silicon layer and a collector contact are formed on a buried collector layer, an oxide dummy pattern is formed on the silicon layer to define both an extrinsic base and an intrinsic base. A polycide layer used as the extrinsic base is formed thereon and selectively removed to expose the dummy pattern. After the exposed dummy pattern is removed, an epitaxial layer used as the intrinsic base is grown on both the silicon layer and the polycide layer, and selectively removed from the top of the polycide layer. An oxide layer and a nitride layer are deposited in sequence thereon, and the nitride layer is blanket-etched to form spacers defining an emitter. After a photoresist pattern is formed to mostly cover the oxide layer and partly expose the oxide layer between the spacers over the intrinsic base, the oxide layer is etched by using the photoresist pattern and the spacers as an etch mask.