Abstract: A thin-film transistor array panel and a manufacturing method thereof are provided for one or more embodiments. The thin-film transistor array panel may include: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a source electrode and a drain electrode formed on the gate insulating layer; and a flatness layer formed on the source electrode and the drain electrode, wherein the drain electrode has a higher height than the flatness layer.

Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

Abstract: A liquid crystal display includes a first display panel including a first substrate, and first and second color filters disposed on the first substrate and adjacent to each other, a second display panel including a second substrate facing the first display panel and a first spacer disposed on the second substrate, and a liquid crystal layer disposed between the first and second display panels. The first color filter includes a first protrusion protruded toward and overlapped with the second color filter. The first spacer faces the first protrusion, and the first and second display panels contact each other at a location area of the first spacer.

Abstract: A display substrate includes a base substrate, a first line, a second line, a bridge line, a thin-film transistor (TFT), a storage line, and a pixel electrode. The first line extends in a first direction on the base substrate. The second line extends in a second direction on the base substrate and is divided into two portions with respect to the first line. The bridge line makes contact with the two portions of the second line in first and second bridge contact regions. The TFT includes a source electrode making contact with one of the first and second lines in a data contact region. The storage line is formed on the one of the first and second lines. The pixel electrode is formed on the storage line and is electrically connected to the TFT. The display substrate reduces formation of parasitic capacitance between pixel electrode and data line.

Abstract: A display panel includes n gate lines, a data line, a first pixel and a second pixel. The gate lines extend in a first direction. The data line extends in a second direction transverse to the first direction. The first pixel includes a first pixel electrode connected to one of the (n?1) gate lines to receive a data voltage through the data line. The second pixel includes a second pixel electrode and a light-blocking pattern. The second pixel electrode is connected to the (n)-th gate line to receive the data voltage through the data line. The light-blocking pattern obscures the second pixel to possibly reduce a luminance difference between the first and second pixels.

Abstract: A display panel includes a plurality of gate lines, a plurality of data lines and a plurality of pixel groups. The gate lines extend in a first direction and sequentially receive gate signals, and the data lines extend in a second direction that is substantially perpendicular to the first direction and receive data signals. Each pixel group includes first, second and third vertical pixels that extend in the second direction and are sequentially arranged in the first direction. The first to third vertical pixels are arranged horizontally and are electrically connected to three consecutive gate lines to receive gate signals, and are connected to two or fewer data lines to receive the data signals.

Abstract: In a liquid crystal display panel, an array substrate includes a pixel electrode including a conductive organic material provided with an alignment pattern formed thereon. The pixel electrode serves as an electrode that receives a pixel voltage and as an alignment layer that aligns liquid crystal molecules. Thus, the array substrate does not need to have a separate alignment layer in order to align the liquid crystal molecules, thereby reducing manufacturing cost and process complexity and enhancing productivity.

Abstract: The present invention relates to a display device. A display device according to an exemplary embodiment of the present invention includes a first substrate, a second substrate facing the first substrate, a sensing electrode disposed on the first substrate or the second substrate, and at least one touch sensor protrusion facing the sensing electrode. The touch sensor protrusion includes an organic material and carbon nanotubes.

Abstract: An array substrate includes a gate line, a data line, a thin film transistor (TFT), a pixel electrode and a storage line. The pixel electrode includes a main pixel electrode and a sub pixel electrode partly surrounding at least a portion of the main pixel electrode. The storage line includes a main storage line that extends substantially parallel to the gate line and across the pixel electrode, a sub storage line that extends from the main storage line and substantially parallel to the data line to overlap the sub pixel electrode, and a protruding storage line that extends from the sub storage line and substantially parallel to the gate line to overlap the main pixel electrode.

Abstract: A liquid crystal display (LCD) device and a method of fabricating the same includes a gate line arranged in one direction, a data line arranged in a perpendicular direction to the gate line, a pixel electrode arranged in a pixel region defined by the gate and data lines and having a diagonal side adjacent to a crossing portion of the gate and data lines, and a light blocking pattern arranged in a parallel direction with respect to the diagonal side of the pixel electrode and preventing light leakage.

Abstract: A color filter substrate having a conductive column spacer and a liquid crystal display panel including the color filter substrate. The color filter substrate includes a transparent insulating substrate, a black matrix arranged on the substrate to block light, a plurality of color filters arranged on the substrate and the black matrix, an overcoat layer arranged on the color filters, a first column spacer arranged on the overcoat layer to maintain a liquid crystal cell gap, and a common electrode arranged on the overcoat layer and the first column spacer. The first column spacer is arranged in a display area of the substrate.

Abstract: A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.

Abstract: A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.

Abstract: A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.

Abstract: The present invention relates to a method of crystallizing an amorphous silicon thin film by thermal annealing the amorphous silicon thin film vapor deposited on a substrate in order to form a polycrystalline silicon thin film, and a semiconductor device fabricated by the method. According to the present invention, it is constructed such that a light-absorbing layer having absorbance of light much higher than that of the substrate or the amorphous silicon thin film is formed around the amorphous silicon thin film and is heated by a lamp when crystallizing the amorphous silicon thin film vapor deposited on the substrate by rapid annealing. Therefore, the temperature of the amorphous silicon thin film can be raised while restraining the increase in temperature of the substrate to the utmost. Accordingly, the amorphous silicon thin film can be crystallized without deformation of the substrate.

Abstract: A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.