Patents by Inventor Yeo Kiat Seng

Yeo Kiat Seng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6777774
    Abstract: A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: August 17, 2004
    Assignee: Chartered Semiconductor Manufacturing Limited
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu, Lap Chan, Chew Kok-Wai
  • Patent number: 6714112
    Abstract: A silicon-based inductor in a semiconductor is disclosed. One embodiment provides for an inductor having a metal region comprising turns. The metal region has spacing between adjacent turns. The width of the spacing varies. The spacing is pre-determined to optimize the performance of the inductor by reducing eddy currents in the turns and reducing eddy currents induced in a substrate. One embodiment provides for an inductor having a spiral structure. The spiral structure may have a number of turns with the spacing between the turns of the inductor being larger near the inside of the spiral structure. A large spacing between the inductor's inner turns may serve to reduce both conductor eddy currents and the induced substrate current. Thus, the structure improves the inductor's overall performance.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: March 30, 2004
    Assignee: Chartered Semiconductor Manufacturing Limited
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu
  • Publication number: 20030210121
    Abstract: A silicon-based inductor in a semiconductor is disclosed. One embodiment provides for an inductor having a metal region comprising turns. The metal region has spacing between adjacent turns. The width of the spacing varies. The spacing is pre-determined to optimize the performance of the inductor by reducing eddy currents in the turns and reducing eddy currents induced in a substrate. One embodiment provides for an inductor having a spiral structure. The spiral structure may have a number of turns with the spacing between the turns of the inductor being larger near the inside of the spiral structure. A large spacing between the inductor's inner turns may serve to reduce both conductor eddy currents and the induced substrate current. Thus, the structure improves the inductor's overall performance.
    Type: Application
    Filed: May 10, 2002
    Publication date: November 13, 2003
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu
  • Publication number: 20030197243
    Abstract: A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.
    Type: Application
    Filed: April 17, 2002
    Publication date: October 23, 2003
    Inventors: Sia Choon Beng, Yeo Kiat Seng, Sanford Chu, Lap Chan, Chew Kok-Wai
  • Patent number: 6417740
    Abstract: A variable frequency signal generator, in the form of a voltage controlled oscillator, provides wide-band and/or multi-band output frequency operation using two control voltage inputs. A pair of LC oscillator circuits are cross-coupled through a transconductance control circuit. The oscillator circuits provide quadrature output frequency signals. The oscillator circuits include MOSFET varactors controllable by a first control voltage which can be used to drive the varactors into inversion or depletion operating modes which correspond to respective output signal frequency bands. A second control voltage is provided to the transconductance control circuit to control currents injected from each oscillator to the other, thereby selecting a particular output frequency within the range of the frequency band determined by the first control voltage.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: July 9, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Do Manh Anh, Zhao Ruiyan, Ma Jian-Guo, Yeo Kiat Seng, Chew Kok Wai