Abstract: An image sensor includes a plurality of pixels and a phase select circuit. Each pixel outputs a pixel signal corresponding to a photoelectric signal in response to a photo gate signal. The phase select circuit outputs delay clock signals of different phases from each other to an object pixel in response to different integration times from each other in a frame. The phase select circuit includes a plurality of delay circuit cells corresponding to at least some pixels of the plurality of pixels. Each of the plurality of delay circuit cells generates a delay clock signal of a certain phase difference from any one of a reference clock signal and an output signal of another delay circuit cell according to a logic state of a select signal.

Abstract: Provided is a time amplifier. The time amplifier includes: an SR latch providing an output at a timing determined according to a time difference between two inputs; and an operation determination unit connected to a power terminal of the SR latch and configured to determine an operation of the SR latch.

Abstract: A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit.

Abstract: A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit.

Abstract: The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

Abstract: Provided is a time amplifier. The time amplifier includes: an SR latch providing an output at a timing determined according to a time difference between two inputs; and an operation determination unit connected to a power terminal of the SR latch and configured to determine an operation of the SR latch.

Abstract: The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

Abstract: Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.

Abstract: Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.