Abstract: A boosting unit comprises a plurality of boosting circuits. Each boosting circuit includes an input driving circuit, a switching circuit, a capacitor circuit, and a precharge circuit. The input driving circuit drives a corresponding external boosting signal. The switching circuit transfers either a power supply voltage, a ground voltage, or a boosting signal from one of the other boosting circuits to the capacitor circuit under the control of the corresponding external boosting signal. The capacitor circuit boosts up a boosting node, which has been precharged to a power supply voltage level by the precharge circuit, to predetermined voltage level higher than an input voltage level. The boosting circuits are connected together in series and simultaneously carry out a boosting operation. The boosting unit therefore provides a desired boosted voltage level at high speed.

Abstract: Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations.

Abstract: Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations.

Abstract: Disclosed is a ferroelectric random access memory having increased endurance and educed power consumption. The ferroelectric random access memory device comprises a bit line precharge circuit for precharging each of the bit lines to a first voltage level, a pulse supply circuit for supplying a first voltage pulse signal to a first electrode of the ferroelectric capacitor corresponding to a selected one of the memory cells for allowing the ferroelectric capacitor to polarize in a predetermined direction, and a drive signal generation circuit for generating two complementary drive signals which vary from a first voltage level to a second voltage level.

Abstract: Variable test voltage circuits and methods are provided for ferroelectric memory devices. The ferroelectric memory devices include a first bit line, a word line, a nonvolatile memory cell at an intersection of the first bit line and the word line, a second bit line corresponding to the first bit line and a sense amplifier connected between the first and second bit lines to sense a voltage difference between the first and second bit lines. Test circuits and methods receive a variable test voltage and force at least one of the first and second bit lines to the variable test voltage in response to control signals during a test mode of operation. The ferroelectric memory may also include a reference cell including a ferroelectric capacitor, wherein the reference cell supplies a reference voltage to the second bit line. The test circuits and methods also may be responsive to deselection of the word line to force the first bit line to the variable test voltage.

Abstract: A ferroelectric memory device with plate line segments free from the capacitive plate line segment coupling in a read/write operation, and a method of accessing the memory device. The memory device includes a floating protection circuit for protecting unselected plate line segments from being floated during a read/write operations. The floating protection circuit prevents data disturbance due to the capacitive plate line segment coupling. In a data write method of the memory device, a sense amplifier corresponding to a bit line is activated after a voltage corresponding to a data bit to the bit line is applied. In a data read method of the memory device, the sense amplifier is activated and then a column gate corresponding to the bit line is selected.

Abstract: Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations.

Abstract: A nonvolatile ferroelectric semiconductor random access memory device and a method for protecting ferroelectric memory cell capacitors from data damage are provided. The contents of the FRAM cells are protected against damage when a power supply voltage goes lower than a predetermined threshold voltage level. Since chip power off time is about several milliseconds and it takes several nanoseconds for a memory chip to perform a normal operation such as a read/write operation, the memory device completes the current read/write operation during either unexpected power down or power off mode, thereby protecting data stored in ferroelectric memory cells against damage when a power supply voltage goes down.