Abstract: An electronic apparatus is provided for obtaining compiling data used in an external processor including a function unit including a plurality of input ports. The electronic apparatus includes a storage configured to store a plurality of instructions, and a processor configured to schedule each of the plurality of instructions in a plurality of cycles, assign a plurality of input data corresponding to the plurality of instructions to the plurality of input ports in a corresponding cycle, and if an unassigned input port among the plurality of input ports is present in a first cycle, assign a part of input data corresponding to an instruction scheduled in a second cycle after the first cycle to the unassigned input port in the first cycle, and obtain the compiling data by assigning remaining data of the input data corresponding the instruction to one of the plurality of input ports in the second cycle.

Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.

Abstract: An electronic apparatus is provided for obtaining compiling data used in an external processor including a function unit including a plurality of input ports. The electronic apparatus includes a storage configured to store a plurality of instructions, and a processor configured to schedule each of the plurality of instructions in a plurality of cycles, assign a plurality of input data corresponding to the plurality of instructions to the plurality of input ports in a corresponding cycle, and if an unassigned input port among the plurality of input ports is present in a first cycle, assign a part of input data corresponding to an instruction scheduled in a second cycle after the first cycle to the unassigned input port in the first cycle, and obtain the compiling data by assigning remaining data of the input data corresponding the instruction to one of the plurality of input ports in the second cycle.

Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.

Abstract: According to a communication network setting method of a wireless communication terminal, wireless communication can be performed with a communication network by reading in advance features related to a communication standard or a communication provider for recognizing a wireless communication network accessible at a current place, detecting features from a wireless communication signal received at the current place, and then setting a modem in a hardware or software scheme according to the features.

Abstract: A method and corresponding apparatus for processing a shuffle instruction are provided. Shuffle units are configured in a hierarchical structure, and each of the shuffle units generates a shuffled data element array by performing shuffling on an input data element array. In the hierarchical structure, which includes an upper shuffle unit and a lower shuffle unit, the shuffled data element array output from the lower shuffle unit is input to the upper shuffle unit as a portion of the input data element array for the upper shuffle unit.

Abstract: Provided is a loop scheduling method including scheduling a first loop using execution units, and scheduling a second loop using execution units available as a result of the scheduling of the first loop. An n-th loop (n>2) may be scheduled using a result of scheduling an (n?1)-th loop, similar to the (n?1)-th loop. The first loop may be a higher priority loop than the second loop.

Abstract: According to a communication network setting method of a wireless communication terminal, wireless communication can be performed with a communication network by reading in advance features related to a communication standard or a communication provider for recognizing a wireless communication network accessible at a current place, detecting features from a wireless communication signal received at the current place, and then setting a modem in a hardware or software scheme according to the features.

Abstract: Provided is a loop scheduling method including scheduling a first loop using execution units, and scheduling a second loop using execution units available as a result of the scheduling of the first loop. An n-th loop (n>2) may be scheduled using a result of scheduling an (n?1)-th loop, similar to the (n?1)-th loop. The first loop may be a higher priority loop than the second loop.

Abstract: A method and corresponding apparatus for processing a shuffle instruction are provided. Shuffle units are configured in a hierarchical structure, and each of the shuffle units generates a shuffled data element array by performing shuffling on an input data element array. In the hierarchical structure, which includes an upper shuffle unit and a lower shuffle unit, the shuffled data element array output from the lower shuffle unit is input to the upper shuffle unit as a portion of the input data element array for the upper shuffle unit.

Abstract: A mini-core and a processor using such a mini-core are provided in which functional units of the mini-core are divided into a scalar domain processor and a vector domain processor. The processor includes at least one such mini-core, and all or a portion of functional units from among the functional units of the mini-core operate based on an operation mode.