Patents by Inventor Yeon CHANG
Yeon CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250133722Abstract: A semiconductor memory device includes a storage pad on a substrate, a lower electrode on the storage pad and including a trench defined by a bottom and sidewalls of the lower electrode, a lower support pattern including a first portion in the trench and a second portion on an upper surface of the lower electrode, an upper support pattern on an upper surface of the lower support pattern, a capacitor dielectric film on the lower electrode, the lower support pattern, and the upper support pattern, and an upper electrode on the capacitor dielectric film.Type: ApplicationFiled: July 19, 2024Publication date: April 24, 2025Inventors: Eui-Hyuk Kim, Ji Yeon Chang, Hyeon Song Cha
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Publication number: 20240243976Abstract: A virtual negative edge-based directed network embedding method and system are disclosed. A network embedding method performed by a network embedding system according to an embodiment may comprise the steps of: searching for a virtual negative edge representing a potentially negative relationship between nodes within a directed network; and performing network embedding for expressing the nodes within the directed network as low-dimensional vectors by using the searched virtual negative edge.Type: ApplicationFiled: April 21, 2022Publication date: July 18, 2024Applicant: IUCF-HYU (Industry University Cooperation Foundation Hanyang University)Inventors: Sang-Wook Kim, Hyun Sik Yoo, Yeon-Chang Lee
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Publication number: 20230395569Abstract: Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative memory device includes a substrate including circuitry, back-end contacts electrically coupled to the circuitry, and front-end contacts. The front-end contacts are configured to receive electrical signals from an external device via a front-end interface. Individual ones of the front-end contacts are electrically coupled to and aligned along an axis with corresponding ones of the back-end contacts.Type: ApplicationFiled: May 25, 2023Publication date: December 7, 2023Inventors: Chin Hui Chong, Hari Giduturi, Yeon-Chang Hahm
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Publication number: 20220351076Abstract: Provided is a personalized node ranking (PNR) system and method using random walk. In detail, a personalized ranking method using random walk includes verifying whether propagation of a positive score or a negative score of a currently-visiting node is trustworthy based on an edge sign between a seed node and a next-visiting node predicted by using a classification model, and when the propagation is trustworthy according to the verification, propagating a score by using a first score propagation method based on balance theory, and when the propagation is untrustworthy according to the verification, propagating a score by using a second score propagation method based on a ratio between a balanced triangle and an unbalanced triangle of a signed network.Type: ApplicationFiled: April 28, 2022Publication date: November 3, 2022Applicant: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Sang Wook KIM, Yeon Chang LEE, Won Chang LEE
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Publication number: 20220230060Abstract: A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.Type: ApplicationFiled: July 5, 2019Publication date: July 21, 2022Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Vladimir KORNIJCUK, Doo Seok JEONG, Joon Young KWAK, Jae Wook KIM, Jong Kil PARK, In Ho KIM, Jong Keuk PARK, Su Youn LEE, Yeon Joo JEONG, Joon Yeon CHANG
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Patent number: 10622490Abstract: Provided is a reconfigurable logic device using an electrochemical potential. The device includes first and second semiconductor channels, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculate a difference value corresponding to a difference between a first determination value and a second determination value, and compare the difference value with a reference value to determine an output value.Type: GrantFiled: March 14, 2018Date of Patent: April 14, 2020Assignee: Korea Institute of Science and TechnologyInventors: Hyun Cheol Koo, Hyung Jun Kim, Cha Un Jang, Joon Yeon Chang, Suk Hee Han, Joo Hyeon Lee
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Publication number: 20190035943Abstract: Provided is a reconfigurable logic device using an electrochemical potential. The device includes first and second semiconductor channels, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculate a difference value corresponding to a difference between a first determination value and a second determination value, and compare the difference value with a reference value to determine an output value.Type: ApplicationFiled: March 14, 2018Publication date: January 31, 2019Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hyun Cheol KOO, Hyung Jun KIM, Cha Un JANG, Joon Yeon CHANG, Suk Hee HAN, Joo Hyeon LEE
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Patent number: 10071908Abstract: The present disclosure provides a burner for a reduction reactor, the reduction reactor has a reaction space formed therein, wherein each burner has a fuel feeding hole and multiple oxygen feeding holes formed therein, wherein each burner has an elongate combustion space formed at one end of a head portion thereof, the combustion space fluid-communicating with the reaction space of the reactor, wherein the elongate combustion space has a length such that oxygen supplied from the oxygen feeding holes thereto is completely consumed via oxidation or combustion with fuels supplied from the fuel feeding hole thereto only in the elongate combustion space upon igniting the burner.Type: GrantFiled: May 13, 2016Date of Patent: September 11, 2018Inventors: Yeon Chang, Sang Won Kim
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Patent number: 10014396Abstract: A spin control electronic device operable at room temperature according to an embodiment of the present invention includes a transfer channel that includes a low-dimensional nanostructure, the nanostructure being located on a substrate, having an elongate shape in a first direction and having a cross section, cut along a second direction that is perpendicular to the first direction, in the shape of a triangle; a source electrode located on the substrate and intersecting the transfer channel, the source electrode covering part of the transfer channel; and a drain electrode spaced apart from the source electrode on the substrate, the drain electrode intersecting the transfer channel and covering part of the transfer channel.Type: GrantFiled: April 14, 2017Date of Patent: July 3, 2018Assignee: Korea Institute of Science and TechnologyInventors: Joon Yeon Chang, Tae Eon Park, Byoung Chul Min, Hyun Cheol Koo, Suk Hee Han
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Publication number: 20170301778Abstract: A spin control electronic device operable at room temperature according to an embodiment of the present invention includes a transfer channel that includes a low-dimensional nanostructure, the nanostructure being located on a substrate, having an elongate shape in a first direction and having a cross section, cut along a second direction that is perpendicular to the first direction, in the shape of a triangle; a source electrode located on the substrate and intersecting the transfer channel, the source electrode covering part of the transfer channel; and a drain electrode spaced apart from the source electrode on the substrate, the drain electrode intersecting the transfer channel and covering part of the transfer channel.Type: ApplicationFiled: April 14, 2017Publication date: October 19, 2017Applicant: Korea Institute of Science and TechnologyInventors: Joon Yeon CHANG, Tae Eon PARK, Byoung Chul MIN, Hyun Cheol KOO, Suk Hee HAN
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Patent number: 9743415Abstract: A system for outputting content through a network includes: a first server configured to store content received in an account of a user; and a second server configured to obtain the content from the first server, convert the content into output data, and transmit the output data to an output device, according to an output request received from a mobile terminal of the user, wherein when the second server receives a request to check the content from the mobile terminal, the second server provides a preview of the content, instead of an original file of the content, to the mobile terminal.Type: GrantFiled: December 16, 2015Date of Patent: August 22, 2017Assignee: S-PRINTING SOLUTION CO., LTD.Inventors: Jeong-jin Park, Yong-chan Kwon, Kasey Kim, Min-jae Kim, Sang-ho Kim, Yoon-bum No, Woo-yeon Chang
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Publication number: 20160370003Abstract: The present disclosure provides a burner for a reduction reactor, the reduction reactor has a reaction space formed therein, wherein each burner has a fuel feeding hole and multiple oxygen feeding holes formed therein, wherein each burner has an elongate combustion space formed at one end of a head portion thereof, the combustion space fluid-communicating with the reaction space of the reactor, wherein the elongate combustion space has a length such that oxygen supplied from the oxygen feeding holes thereto is completely consumed via oxidation or combustion with fuels supplied from the fuel feeding hole thereto only in the elongate combustion space upon igniting the burner.Type: ApplicationFiled: May 13, 2016Publication date: December 22, 2016Inventor: Yeon CHANG
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Publication number: 20160219575Abstract: A system for outputting content through a network includes: a first server configured to store content received in an account of a user; and a second server configured to obtain the content from the first server, convert the content into output data, and transmit the output data to an output device, according to an output request received from a mobile terminal of the user, wherein when the second server receives a request to check the content from the mobile terminal, the second server provides a preview of the content, instead of an original file of the content, to the mobile terminal.Type: ApplicationFiled: December 16, 2015Publication date: July 28, 2016Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-jin PARK, Yong-chan KWON, Kasey KIM, Min-jae KIM, Sang-ho KIM, Yoon-bum NO, Woo-yeon CHANG
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Patent number: 9331266Abstract: A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.Type: GrantFiled: December 18, 2013Date of Patent: May 3, 2016Assignees: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY, THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE NAVYInventors: Joon Yeon Chang, Jin Ki Hong, Jin Dong Song, Mark Johnson
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Patent number: 9099328Abstract: A complementary device including a gate electrode, a channel, a source electrode connected to the gate electrode and the channel, and a first drain electrode and a second drain electrode connected to the gate electrode and the channel is provided. The first/second drain electrode is formed so that, in accordance with a voltage applied to the gate electrode, electron spins injected into the source electrode are moved from the source electrode to the first/second drain electrode through the channel while rotating in a first/second direction. Directions of the electron spins that reach the first drain electrode and the second drain electrode are opposite to each other.Type: GrantFiled: October 11, 2013Date of Patent: August 4, 2015Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hyun Cheol Koo, Hyung-Jun Kim, Joon Yeon Chang, Jun Woo Choi, Suk Hee Han
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Publication number: 20140264514Abstract: A complementary device including a gate electrode, a channel, a source electrode connected to the gate electrode and the channel, and a first drain electrode and a second drain electrode connected to the gate electrode and the channel is provided. The first/second drain electrode is formed so that, in accordance with a voltage applied to the gate electrode, electron spins injected into the source electrode are moved from the source electrode to the first/second drain electrode through the channel while rotating in a first/second direction. Directions of the electron spins that reach the first drain electrode and the second drain electrode are opposite to each other.Type: ApplicationFiled: October 11, 2013Publication date: September 18, 2014Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hyun Cheol KOO, Hyung-Jun KIM, Joon Yeon CHANG, Jun Woo CHOI, Suk Hee HAN
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Publication number: 20140167814Abstract: A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.Type: ApplicationFiled: December 18, 2013Publication date: June 19, 2014Applicants: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Joon Yeon CHANG, Jin Ki HONG, Jin Dong SONG, Mark JOHNSON
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Patent number: 8624026Abstract: Disclosed are a novel, simple and low-cost method for preparing sitagliptin of formula (I), as DPP-IV (dipeptidyl peptidase IV) inhibitor, which is useful in treating type 2 diabetes mellitus and key intermediates used in said preparation of sitagliptin:Type: GrantFiled: October 19, 2010Date of Patent: January 7, 2014Assignee: Hanmi Science Co., LtdInventors: Nam Du Kim, Ji Yeon Chang, Dong Jun Kim, Hyun Seung Lee, Jae Hyuk Jung, Young Kil Chang, Gwan Sun Lee
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Patent number: 8587044Abstract: A complementary logic device includes: an insulating layer formed on a substrate; a source electrode formed of a ferromagnetic body on the insulating layer; a gate insulating film; a gate electrode formed on the gate insulating film and controlling a magnetization direction of the source electrode; a channel layer formed on each of a first side surface and a second side surface of the source electrode and transmitting spin-polarized electrons from the source electrode; a first drain electrode formed on the first side surface of the source electrode; and a second drain electrode formed on the second side surface of the source electrode, wherein a magnetization direction of the first drain electrode and a magnetization direction of the second drain electrode are antiparallel to each other. Therefore, not only characteristics of low power and high speed but also characteristics of non-volatility and multiple switching by spin may be obtained.Type: GrantFiled: November 2, 2012Date of Patent: November 19, 2013Assignee: Korea Institute of Science and TechnologyInventors: Hyun Cheol Koo, Hyung Jun Kim, Joon Yeon Chang, Suk Hee Han, Hi Jung Kim
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Patent number: 8421060Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.Type: GrantFiled: January 8, 2010Date of Patent: April 16, 2013Assignee: Korea Institute of Science and TechnologyInventors: Hyun Cheol Koo, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim, Jang Hae Ku