Abstract: A region growing apparatus using multi-core includes a plurality of cores, each core including an operation controller configured to perform an operation for region growing of a 2D pixel region or 3D pixel region and an inner memory configured to store a queue associated with a seed pixel as a target of the operation; and a shared memory connected to the plurality of cores over a network and shared by the plurality of cores.

Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Abstract: An apparatus and method for graphics state management. The apparatus for graphics state management includes a state version manager configured to manage changes in graphics state versions by allocating or deallocating a memory for each of graphics states based on a page of a predetermined size, wherein the state version manager allocates or deallocates pages for each of the graphics state versions by using a string of binary values that indicates the respective reference states of each of those pages.

Abstract: An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.

Abstract: An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information.

Abstract: A functional unit for supporting multithreading, a processor including the same, and an operating method of the processor are provided. The functional unit for supporting multithreading includes a plurality of input ports configured to receive opcodes and operands for a plurality of threads, wherein each of the plurality of input ports is configured to receive an opcode and an operand for a different thread, a plurality of operators configured to perform operations using the received operands, an operator selector configured to select, based on each opcode, an operator from among the plurality of operators to perform a specific operation using an operand from among the received operands, and a plurality of output ports configured to output operation results of operations for each thread.

Abstract: Provided are a multi-thread processing apparatus and method for sequentially processing threads. The multi-thread processing method includes scheduling, at a processor, one of a plurality of thread groups allocated by a job distributor, determining whether the thread group has been initialized based on an examination an uninitialized flag of the scheduled thread group, generating a thread group descriptor for the scheduled thread group and initializing the thread group based on the determination of whether the thread group has been initialized, and initializing a thread descriptor based on a determination of whether initialization is needed and sequentially executing each thread in the scheduled thread group.

Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

Abstract: A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.

Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Abstract: An apparatus and method for supporting a multi-mode. The apparatus for supporting a multi-mode may include an instruction distributor configured to select, according to a current execution mode, at least one instruction from among a plurality of received instructions that each include an operand and an opcode, and transfer the opcode included in each of at least one selected instruction to the plurality of functional units; an operand switch controller configured to generate, based on the operand included in each of the selected at least one instruction, switch configuration information for routing in order to execute the selected at least one instruction; and an operand switch configured to route, based on the switch configuration information, a functional unit output or a register file output to either a functional unit input or a register file input.

Abstract: A processor for batch thread processing includes a central register file, and one or more function unit batches each including two or more function units and one or more ports to access the central register file. The function units of the function unit batches execute an instruction batch including one or more instructions to sequentially execute the one or more instructions in the instruction batch.

Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

Abstract: A method of compiling a program to be executed on a multicore processor is provided. The method may include generating an initial solution by mapping a task to a source processing element (PE) and a destination PE, and selecting a communication scheme for transmission of the task from the source PE to the destination PE, approximately optimizing the mapping and communication scheme included in the initial solution, and scheduling the task, wherein the communication scheme is designated in a compiling process.

Abstract: Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.

Abstract: A region growing apparatus using multi-core includes a plurality of cores, each core including an operation controller configured to perform an operation for region growing of a 2D pixel region or 3D pixel region and an inner memory configured to store a queue associated with a seed pixel as a target of the operation; and a shared memory connected to the plurality of cores over a network and shared by the plurality of cores.

Abstract: A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.

Abstract: An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.

Abstract: Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program.