Abstract: Disclosed is an edge management unit of accessing a memory including a first memory area and a second memory area. The edge management unit comprises an edge write controller writing bucket information corresponding to input edge data in the first memory area and the edge data at a location of the second memory area appointed by the bucket information; and an edge read controller responding to a scan line signal to read the bucket information from the first memory area and the edge data from a location of the second memory area appointed by the read bucket information.

Abstract: Disclosed is an edge management unit of accessing a memory including a first memory area and a second memory area. The edge management unit comprises an edge write controller writing bucket information corresponding to input edge data in the first memory area and the edge data at a location of the second memory area appointed by the bucket information; and an edge read controller responding to a scan line signal to read the bucket information from the first memory area and the edge data from a location of the second memory area appointed by the read bucket information.

Abstract: A geometry processor of a three-dimensional graphic accelerator may include a storage unit storing vertex data and an index corresponding to the vertex data, a vertex shader geometrically processing the vertex data provided from the storage unit, a vertex cache storing vertex data geometrically processed by the vertex shader, and/or an input processing unit receiving vertex data from a central processing unit to determine whether the geometrically processed vertex data corresponding to the vertex is present in the vertex cache.