Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.

Abstract: A magnetic memory device may include a substrate, an data storage pattern disposed on the substrate, and a lower contact plug between the substrate and the data storage pattern, the lower contact plug may include a lower insulating pattern, a lower contact pattern on the lower insulating pattern, and a lower barrier pattern extending along a lower surface and a side surface of the lower insulating pattern and a side surface of the lower contact pattern.

Abstract: A semiconductor device includes active regions, gate structures intersecting the active regions and including gate electrodes, source/drain regions on the active regions on sides of the gate structures, and a gate isolation structure isolating gate structures, which oppose each other, from each other on a region between the active regions. The gate structures that oppose each other include a first gate structure, a second gate structure opposing the first gate structure, a third gate structure extending in parallel to the first gate structure, and a fourth gate structure opposing the third gate structure and extending in parallel to the second gate structure. The gate isolation structure includes a first isolation structure of a line type extending in the first horizontal direction, and second isolation structures of a hole type penetrating through the first isolation structure between the first and second gate structures and between the third and fourth gate structures.

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

Abstract: A semiconductor device may include a substrate including first and second active regions, which are adjacent to each other, first and second active patterns provided on the first and second active regions, respectively, and a gate electrode extended to cross the first and second active patterns. The gate electrode may include first and second electrode portions provided on the first and second active regions, respectively. The second electrode portion may include a first metal pattern, an etch barrier pattern, a second metal pattern, and a third metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etch barrier pattern may be in contact with the first metal pattern and the second metal pattern, and the etch barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern.

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns on the first and second active regions, and a gate electrode crossing the first and second active patterns. The gate electrode may include first and second electrode portions on the first and second active regions. The first electrode portion may include a first metal pattern and a second metal pattern on the first metal pattern. The second electrode portion may include a third metal pattern and a fourth metal pattern on the third metal pattern. The first metal pattern may include a first line portion and a first vertical portion extended from the first line portion, and the third metal pattern may include a second line portion and a second vertical portion extended from the second line portion. The first and second vertical portions may be in contact with each other.

Abstract: An integrated circuit semiconductor device includes a first region including first active fins extending in a first direction, and first transistors including first gate electrodes extending in a second direction, a second region in contact with the first region in the second direction, wherein the second region includes second active fins extending in the first direction, and second transistors including second gate electrodes extending in the second direction. The integrated circuit semiconductor device includes metal dams at a boundary of the first region and the second region to separate the first gate electrodes and the second gate electrodes in the second direction, wherein the metal dams, the first gate electrodes, and the second gate electrodes are electrically connected in the second direction.

Abstract: A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern.

Abstract: A semiconductor device includes a substrate including a first active fin and a second active fin respectively extending in a first direction, the substrate having a recess between the first and second active fins, a device isolation film on the substrate, first and second gate structures on the first and second active fins, respectively, and extending in a second direction, and a field separation layer having a first portion between the first and second active fin and in the recess, and a second portion extending from both sides of the first portion in the second direction to an upper surface of the device isolation film. The recess has a bottom surface lower in a third direction intersecting the first direction and the second direction than the upper surface of the device isolation film, and a region of the upper surface of the device isolation film has a flat surface.

Abstract: A semiconductor memory device includes: a substrate having a first channel structure and a second channel structure respectively extending in a first direction and arranged in a second direction perpendicular to the first direction; a first gate structure disposed on the first channel structure and extending in the second direction on the substrate; a second gate structure disposed on the second channel structure and extending in the second direction; first source/drain regions respectively disposed on opposite sides of the first gate structure; second source/drain regions respectively disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the first and second gate structures and having an upper surface at a level lower than that of an upper surface of each of the first and second gate structures, the gate separation pattern including a first insulating material; and a gate capping layer disposed on the first and second gate structures and having an extension porti

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

Abstract: Disclosed is an artificial intelligence voice recognition apparatus including: an audio input unit configured to receive a voice; a communication module configured to transmit voice data received from the audio input unit to a server system, which performs voice recognition processing, and receive recognition result data on the voice data from the server system; and a controller configured to control the audio input unit and the communication module, wherein, when a voice command in the voice data corresponds to a pre-stored keyword command, the controller performs control to perform an operation corresponding to the keyword command, and wherein when the voice command in the voice data does not correspond to the pre-stored keyword command, the controller performs control to transmit the voice data including the voice command to the server system. Accordingly, voice recognition may be performed efficiently.

Abstract: Disclosed is a voice recognition apparatus including: an audio input unit configured to receiving a voice; a communication module configured to transmit voice data received from the audio input unit to a server system which performs voice recognition processing, and receive recognition result data on the voice data from the server system; and a controller configured to control the audio input unit and the communication module, wherein, when first voice data is received, the controller perform control to transmit the first voice data to the server system, and wherein, when the first voice data is a conversation command, the controller performs control to receive a first audible answer message including a first question from the server system and output the first audible answer message. In this manner, voice recognition may be performed efficiently.

Abstract: Disclosed is a voice recognition apparatus including: an audio input unit configured to receive a voice; a communication module configured to transmit voice data received from the audio input unit to a server system, which performs voice recognition processing, and receive recognition result data on the voice data from the server system; and a controller configured to control the audio input unit and the communication module, wherein, when a voice command in the voice data corresponds to a pre-stored keyword command, the controller performs control to perform an operation corresponding to the keyword command, and wherein when the voice command in the voice data does not correspond to the pre-stored keyword command, the controller performs control to transmit the voice data including the voice command to the server system. Accordingly, voice recognition may be performed efficiently.

Abstract: A mobile terminal is disclosed herein. The mobile terminal may include a body, a display, a transceiver for short range radio communication, and a controller configured to control data transfer through the transceiver. The controller may be configured to determine whether a request for data is received, determine whether an input is required to allow authorize the data transfer, and determine whether the data transfer is authorized, and transfer data through the transceiver when the data transfer is authorized. The input may be received without displaying a prompt on the display for the input. The input may be received while the display is turned off. Moreover, the input may be a prescribed movement of the body of the mobile terminal or an application of a prescribed amount of force on the mobile terminal.

Abstract: A mobile terminal is disclosed herein. The mobile terminal may include a body, a display, a transceiver for short range radio communication, and a controller configured to control data transfer through the transceiver. The controller may be configured to determine whether a request for data is received, determine whether an input is required to allow authorize the data transfer, and determine whether the data transfer is authorized, and transfer data through the transceiver when the data transfer is authorized. The input may be received without displaying a prompt on the display for the input. The input may be received while the display is turned off. Moreover, the input may be a prescribed movement of the body of the mobile terminal or an application of a prescribed amount of force on the mobile terminal.

Abstract: A mobile terminal is disclosed herein. The mobile terminal may include a body, a display, a transceiver for short range radio communication, and a controller configured to control data transfer through the transceiver. The controller may be configured to determine whether a request for data is received, determine whether an input is required to allow authorize the data transfer, and determine whether the data transfer is authorized, and transfer data through the transceiver when the data transfer is authorized. The input may be received without displaying a prompt on the display for the input. The input may be received while the display is turned off. Moreover, the input may be a prescribed movement of the body of the mobile terminal or an application of a prescribed amount of force on the mobile terminal.