Abstract: A method for replicating a holographic optical element and a holographic optical element replicated thereby are provided. The holographic optical element is larger than a master. The master has a holographic grating pattern generated on the master by interference of the reflected, diffracted or transmitted beam generated by irradiating the master having a specific diffraction grating pattern formed thereon with a laser beam.

Abstract: Provided are a scalable analog passive intermodulation (PIM) module, a method of controlling analog PIM, a signal processing circuit, and a sensor device. The scalable analog PIM module includes a first plural number of digital-to-analog converters (DACs), a first plural number of static random access memory (SRAM) calculators connected to the first plural number of DACs, at least one analog-to-digital converter (ADC) connected to the first plural number of SRAM calculators and configured to convert an analog convolution result signal into digital convolution data, and an analog PIM controller configured to output an enable control signal for enabling a second number, which is equal to or less than first plural number, of SRAM calculators among the first plural number of SRAM calculators to the first plural number of SRAM calculators on the basis of the convolution data output from the ADC.

Abstract: A technology related to a power amplifier used in a wireless communication circuit is disclosed. A radio frequency (RF) power amplifier includes a plurality of unit differential amplifiers of which inputs are connected to a common input terminal and outputs are connected to a common adder, and having a gain of a weight of a corresponding bit of a binary gain control word. Each of the differential amplifiers may be configured as a complementary metal-oxide semiconductor (CMOS) differential cascode amplifier. In addition, the RF power amplifier may include a structure in which a plurality of attenuators of the same structure are cascade-connected so that an attenuation rate may be linearly and digitally controlled and an output of each attenuator is connected to an output adder through differential buffers of which turn-on and turn-off are controlled by a controller.

Abstract: Disclosed are an artificial intelligence algorithm-based wireless power transmitter, wireless power receiver, and wireless power charging system that are capable of high-speed response to environmental changes and that can optimize the power efficiency of a wireless power receiver, estimate a dynamic location from a signal received from the wireless power receiver using artificial intelligence technology, and dynamically transmit wireless power to a prioritized wireless power receiver according to a power state.

Abstract: According to an embodiment, a method for preparing an amorphous polypropylene copolymer comprises injecting a volume of hexane into a nitrogen-purged reactor, the volume of the hexane corresponding to 20% to 80% of a volume of the reactor, injecting, into the reactor, and mixing an amount of alkyl cocatalyst, the amount of the alkyl cocatalyst corresponding to 1 to 50 times a weight of a primary catalyst, injecting the primary catalyst into the reactor, stirring, and then injecting a molecular weight regulator; and injecting propylene and a monomer for copolymerization into the reactor at a temperature ranging from 40° C. to 90° C.

Abstract: According to the present invention, there is provided a method for preparing low molecular weight amorphous polypropylene. In contrast to the prior art in which amorphous polypropylene is prepared by injecting an internal donor and an external donor upon preparing a primary catalyst, the present invention enables easier preparation of low molecular weight amorphous polypropylene and a copolymer thereof by simply mixing a primary catalyst with an alkylaluminum-based co-catalyst without injecting an internal donor, upon preparing a primary catalyst, and an external donor, upon polymerization. According to the present invention, the primary catalyst has superior reactivity with hydrogen, as chain transfer agent, allowing for preparation of low molecular weight amorphous polypropylene even under low hydrogen pressures and low-pressure driving conditions.

Abstract: According to the present invention, there is provided a method for preparing low molecular weight amorphous polypropylene. In contrast to the prior art in which amorphous polypropylene is prepared by injecting an internal donor and an external donor upon preparing a primary catalyst, the present invention enables easier preparation of low molecular weight amorphous polypropylene and a copolymer thereof by simply mixing a primary catalyst with an alkylaluminum-based co-catalyst without injecting an internal donor, upon preparing a primary catalyst, and an external donor, upon polymerization. According to the present invention, the primary catalyst has superior reactivity with hydrogen, as chain transfer agent, allowing for preparation of low molecular weight amorphous polypropylene even under low hydrogen pressures and low-pressure driving conditions.

Abstract: A receiver includes a mixer configured to convert a radio frequency (RF) signal into a baseband, an impedance shaping unit configured to shape a magnitude of load impedance seen in an output terminal of the mixer in a frequency band of an interference signal converted into the baseband so as to reduce the magnitude of the load impedance, and a trans-impedance amplifier configured to amplify the signal converted into the baseband.

Abstract: A receiver includes a mixer configured to convert a radio frequency (RF) signal into a baseband, an impedance shaping unit configured to shape a magnitude of load impedance seen in an output terminal of the mixer in a frequency band of an interference signal converted into the baseband so as to reduce the magnitude of the load impedance, and a trans-impedance amplifier configured to amplify the signal converted into the baseband.

Abstract: A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

Abstract: Semiconductor devices according to the present invention include a duty cycle correction circuit having a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

Abstract: A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.

Abstract: A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.