Abstract: A semiconductor device and method is providing having a memory cell array divided into a plurality of sectors and an erasing operation is preferably performed by sectors. The sectors are sub-divided into two or more sub-sectors, and at least one word line inside each of the sub-sectors is commonly coupled to another word line inside a different sub-sector. Thus, a plurality of word lines can be commonly coupled to a single word line decoder. Accordingly, a number of required word line decoders for the semiconductor device is reduced. Further, size and power requirements of the semiconductor device can be reduced.

Abstract: A high speed data access apparatus for memory allows only a first page data to perform normal mode access during initial operation, by means of latch control signal generation using a page address signal, and the accompanying page data to practice a page mode access. The apparatus realizes a high speed data access.

Abstract: An address buffer capable of preventing malfunctions of a memory device or preventing delay of the signal outputted from the output buffer by blocking noise, which inverts or blocks the signal outputted from the address signal input unit according to a PMOS control signal and an NMOS control signal, and latches the signal outputted from the clock inverter in the latch unit. The PMOS and the NMOS control signals are outputted to the clock inverter by logically operating the control signal outputted from the control signal generating unit according to the output signal of the latch unit, thereby blocking a noise generated in the address input unit by the signal outputted from the output buffer by the clock inverter.