Abstract: A neutralization/water separation device for an esterified product including: a neutralization tank in which a crude product mixture containing alcohol and an ester compound, a neutralizing agent, and water are put to produce a neutralized mixture; a water separation tank disposed below the neutralization tank to divide the neutralization mixture into a floating layer and an aqueous layer; a partition wall extending downward from a ceiling of the water separation tank to provide a lower passage in the water separation tank; and a transfer line that transfers the neutralized mixture from the neutralization tank to the water separation tank, where the water separation tank includes: a first water separation part into which the neutralized mixture is introduced from the neutralization tank through the transfer line; and a second water separation part into which the neutralized mixture is introduced from the first water separation part through the lower passage, where the first water separation part and the secon

Abstract: The inventive concept provides a teaching method for teaching a transfer position of a transfer robot. The teaching method includes: searching for an object on which a target object to be transferred by the transfer robot is placed, based on a 3D position information acquired by a first sensor; and acquiring coordinates of a second direction and coordinates of a third direction of the object based on a data acquired from a second sensor which is a different type from the first sensor.

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

Abstract: An automatic vending apparatus and an advertisement method thereof are provided. The automatic vending apparatus receives advertisement content and an advertisement schedule through a network, stores the received information, and replays the stored advertisement content on a touch screen in accordance with the stored advertisement schedule. Since it is possible to provide advertisement through automatic vending apparatuses according to a predetermined, advertisement can be provided in a more systematic, various and efficient manner.

Abstract: A multi-port SRAM includes a data latch unit for latching an external data signal in accordance with a write signal from a write word line driver; a driving unit for transmitting a data signal from the data latch unit; a plurality of ports commonly connected to the driving unit for receiving the data signal and for outputting data to a plurality of read bit lines and a plurality of read bit bar lines, respectively, in accordance with a plurality of signals from a read word line driver, respectively; and a control unit for controlling an operation of the driving unit in accordance with the plurality of signals from the read word line driver.

Abstract: A high speed two-port Static Random Access Memory (SRAM) circuit with a write-through function includes a write-through unit receiving data signals DATA, DATAB outputted from a memory cell, carrying out a write-through operation, and outputting first to third signals S1, S2, S3, a data equalizer for equalizing the data signal DATA and the data bar signal DATAB in accordance with an externally generated data line equalizing signal DLEQ, a sense amplifier sensing the data signal DATA and the data bar signal DATAB and amplifying the sensed signals, a switching unit pre-amplifying the data signal DATA and the data bar signal DATAB received via the sense amplifier in accordance with an externally generated read enable signal RE and the first and second signals S1, S2 outputted from the write-through unit, and an output selection unit selecting the third signal S3 from the write-through unit or an output signal of the sense amplifier, in accordance with the first signal S1 outputted from the write-through unit.

Abstract: A power down circuit and method of a sense amplifier for a semiconductor memory device prevents undesirable power consumption by detecting when sensing is completed in the sense amplifier and inhibiting a power supply current flow to the sense amplifier after the detection. The power down circuit includes a data comparator for comparing data outputs from a sense amplifier to inhibit the supply current of the sense amplifier by detecting the sensing operation completion in the sense amplifier, a data latch unit for latching the comparison result from the data comparator, a data enable/reset unit for outputting or resetting the latched comparison result, and a power down unit for turning on or off the sense amplifier circuit based on the comparison result outputted from the data enable/reset unit.