Abstract: A panel control circuit configured to control a display panel includes a plurality of pixels. The panel control circuit includes a controller configured to output an image data and a source driver, including an output circuit and an output control circuit, configured to generate data signals based on the image data. The controller is configured to output an output change signal for changing an output of the source driver. The output circuit is configured to output the data signals to the display panel, and the output control circuit is configured to output an adjusting current to the output circuit in a signal transition section of the output change signal.

Abstract: A panel control circuit configured to control a display panel includes a plurality of pixels. The panel control circuit includes a controller configured to output an image data and a source driver, including an output circuit and an output control circuit, configured to generate data signals based on the image data. The controller is configured to output an output change signal for changing an output of the source driver. The output circuit is configured to output the data signals to the display panel, and the output control circuit is configured to output an adjusting current to the output circuit in a signal transition section of the output change signal.

Abstract: A driving device of a flat panel display configured to receive an image signal and a clock signal includes a driving circuit configured to convert the image signal into pixel data and output the pixel data, a timing controller configured to generate and output a vertical synchronization signal, a horizontal synchronization signal, a source change enable signal, and a display enable signal using the image signal and the clock signal, an output buffer including an input terminal configured to receive the pixel data and an output terminal connected to the flat panel display, and a buffer controller connected to the timing controller and the output buffer and configured to control a bias current, applied to the output buffer, to be decreased by a value during a period.

Abstract: A display driving device for driving a display panel includes a first driving circuit configured to output a first image signal, a second driving circuit configured to output a second image signal, a first switch circuit connected to the first driving circuit, and configured to transmit the first image signal to a part of a first set of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval, and a second switch circuit connected to the second driving circuit, and configured to transmit the second image signal to a part of a second set of sub-pixels arranged in the display panel adjacent to the first set of sub-pixels based on a second switching signal during the first horizontal time interval, wherein a width of the first switching signal and a width of the second switching signal in the first horizontal time differ from each other.

Abstract: A display driving device for driving a display panel includes a first driving circuit configured to output a first image signal, a second driving circuit configured to output a second image signal, a first switch circuit connected to the first driving circuit, and configured to transmit the first image signal to a part of a first set of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval, and a second switch circuit connected to the second driving circuit, and configured to transmit the second image signal to a part of a second set of sub-pixels arranged in the display panel adjacent to the first set of sub-pixels based on a second switching signal during the first horizontal time interval, wherein a width of the first switching signal and a width of the second switching signal in the first horizontal time differ from each other.

Abstract: A driving device of a flat panel display configured to receive an image signal and a clock signal includes a driving circuit configured to convert the image signal into pixel data and output the pixel data, a timing controller configured to generate and output a vertical synchronization signal, a horizontal synchronization signal, a source change enable signal, and a display enable signal using the image signal and the clock signal, an output buffer including an input terminal configured to receive the pixel data and an output terminal connected to the flat panel display, and a buffer controller connected to the timing controller and the output buffer and configured to control a bias current, applied to the output buffer, to be decreased by a value during a period.