Patents by Inventor Yeon-Seong HWANG

Yeon-Seong HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10447252
    Abstract: A level shifter includes (a) an input unit including (i) a first input transistor configured to receive a first voltage and connected to a first connection node, and (ii) a second input transistor configured to receive the first voltage and connected to a second connection node, (b) an output unit including (i) a first output transistor connected to a first output terminal and configured to receive a second voltage, and (ii) a second output transistor connected to a second output terminal and configured to receive the second voltage, (c) a first bias unit configured to control voltage drop between the output terminals and the connection nodes based on a first bias signal, and (d) a second bias unit configured to control a first voltage drop between the first output transistor and the second output terminal and a second voltage drop between the second output transistor and the first output terminal based on a second bias signal.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 15, 2019
    Assignee: DB HiTek Co., Ltd.
    Inventor: Yeon Seong Hwang
  • Publication number: 20190097614
    Abstract: A level shifter includes (a) an input unit including (i) a first input transistor configured to receive a first voltage and connected to a first connection node, and (ii) a second input transistor configured to receive the first voltage and connected to a second connection node, (b) an output unit including (i) a first output transistor connected to a first output terminal and configured to receive a second voltage, and (ii) a second output transistor connected to a second output terminal and configured to receive the second voltage, (c) a first bias unit configured to control voltage drop between the output terminals and the connection nodes based on a first bias signal, and (d) a second bias unit configured to control a first voltage drop between the first output transistor and the second output terminal and a second voltage drop between the second output transistor and the first output terminal based on a second bias signal.
    Type: Application
    Filed: January 30, 2018
    Publication date: March 28, 2019
    Inventor: Yeon Seong HWANG
  • Patent number: 9578268
    Abstract: Provided are a ramp signal calibration apparatus and method and image sensor including the apparatus. The apparatus includes: an analog-to-digital converter (ADC) including a trimmable transistor having a gain value that varies according to stored data, and configured to receive a ramp signal in a state where the gain value is a first gain value, and to output first and second output signals; a subtractor configured to calculate a difference between the first and second output signals; a digital comparator configured to compare the difference with a reference value and to determine whether a slope of the ramp signal has changed; and a counter configured to change the stored data based on whether the slope of the ramp signal has changed, wherein when the counter changes the data, the first gain value of the trimmable transistor is changed to a second gain value according to the changed data.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 21, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Dongguk University Industry-Academic Cooperation Foundation
    Inventors: Dae-Yun Kim, Min-Kyu Song, Yeon-Seong Hwang, Jae-Jung Park
  • Publication number: 20150350585
    Abstract: Provided are a ramp signal calibration apparatus and method and image sensor including the apparatus. The apparatus includes: an analog-to-digital converter (ADC) including a trimmable transistor having a gain value that varies according to stored data , and configured to receive a ramp signal in a state where the gain value is a first gain value, and to output first and second output signals; a subtractor configured to calculate a difference between the first and second output signals; a digital comparator configured to compare the difference with a reference value and to determine whether a slope of the ramp signal has changed; and a counter configured to change the stored data based on whether the slope of the ramp signal has changed, wherein when the counter changes the data, the first gain value of the trimmable transistor is changed to a second gain value according to the changed data.
    Type: Application
    Filed: February 18, 2015
    Publication date: December 3, 2015
    Applicants: SAMSUNG ELECTRONICS CO., LTD., Dongguk University Industry-Academic Cooperation Foundation
    Inventors: Dae-Yun KIM, Min-Kyu SONG, Yeon-Seong HWANG, Jae-Jung PARK