Patents by Inventor Yeon Sik LEE

Yeon Sik LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939698
    Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: March 26, 2024
    Assignee: SENIC INC.
    Inventors: Jong Hwi Park, Jung-Gyu Kim, Eun Su Yang, Byung Kyu Jang, Jung Woo Choi, Yeon Sik Lee, Sang Ki Ko, Kap-Ryeol Ku
  • Publication number: 20240099114
    Abstract: A display device may include a first electrode, a second electrode, an emission layer, an intervening layer, and a first encapsulation layer. The second electrode may overlap the first electrode. The emission layer may be disposed between the first electrode and the second electrode, may overlap the first electrode, and may include a light emitting material. The intervening layer may directly contact the second electrode, may be spaced from each of the first electrode and the emission layer, and may include a fluorine compound. A first section of the first encapsulation layer may overlap the emission layer. The intervening layer may be positioned between the second electrode and a second section of the first encapsulation layer.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: Jae Sik KIM, Jae Ik KIM, Jung Sun PARK, Seung Yong SONG, Duck Jung LEE, Yeon Hwa LEE, Joon Gu LEE, Kyu Hwan HWANG
  • Publication number: 20240076799
    Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.
    Type: Application
    Filed: November 1, 2023
    Publication date: March 7, 2024
    Applicant: SENIC INC.
    Inventors: Jong Hwi PARK, Jung-Gyu KIM, Eun Su YANG, Byung Kyu JANG, Jung Woo CHOI, Yeon Sik LEE, Sang Ki KO, Kap-Ryeol KU
  • Patent number: 11566344
    Abstract: A wafer having relaxation moduli different by 450 GPa or less, as determined by dynamic mechanical analysis, when loaded to 1 N and 18 N with a loading rate of 0.1 N/min at a temperature of 25° C.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 31, 2023
    Assignee: SENIC INC.
    Inventors: Jong Hwi Park, Jongmin Shim, Eun Su Yang, Yeon Sik Lee, Byung Kyu Jang, Jung Woo Choi, Sang Ki Ko, Kap-Ryeol Ku, Jung-Gyu Kim
  • Patent number: 11474012
    Abstract: A method for preparing a SiC ingot includes: disposing a raw material and a SiC seed crystal facing each other in a reactor having an internal space; subliming the raw material by controlling a temperature, a pressure, and an atmosphere of the internal space; growing the SiC ingot on the seed crystal; and collecting the SiC ingot after cooling the reactor. The wafer prepared from the ingot, which is prepared from the method, generates cracks when an impact is applied to a surface of the wafer, the impact is applied by an external impact source having mechanical energy, and a minimum value of the mechanical energy is 0.194 J to 0.475 J per unit area (cm2).
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 18, 2022
    Assignee: SENIC INC.
    Inventors: Jong Hwi Park, Jongmin Shim, Eun Su Yang, Yeon Sik Lee, Byung Kyu Jang, Jung Woo Choi, Sang Ki Ko, Kap-Ryeol Ku, Jung-Gyu Kim
  • Publication number: 20210388527
    Abstract: A wafer having relaxation moduli different by 450 GPa or less, as determined by dynamic mechanical analysis, when loaded to 1 N and 18 N with a loading rate of 0.1 N/min at a temperature of 25° C.
    Type: Application
    Filed: March 5, 2021
    Publication date: December 16, 2021
    Applicant: SKC Co., Ltd.
    Inventors: Jong Hwi PARK, Jongmin SHIM, Eun Su YANG, Yeon Sik LEE, Byung Kyu JANG, Jung Woo CHOI, Sang Ki KO, Kap-Ryeol KU, Jung-Gyu KIM
  • Publication number: 20210372005
    Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.
    Type: Application
    Filed: November 3, 2020
    Publication date: December 2, 2021
    Applicant: SKC Co., Ltd.
    Inventors: Jong Hwi PARK, Jung-Gyu KIM, Eun Su YANG, Byung Kyu JANG, Jung Woo CHOI, Yeon Sik LEE, Sang Ki KO, Kap-Ryeol KU
  • Publication number: 20210272793
    Abstract: An epitaxial wafer including a wafer having one surface and an other surface, and an epitaxial layer formed on the one surface of the wafer, wherein a roughness skewness (Rsk) of the one surface is ?3 nm to 3 nm, and a roughness average (Ra) of an edge area of the one surface is different from that of a central area of the one surface by ?2 nm to 2 nm when the edge area of the one surface is defined as an area between 13.3% and 32.1% of the radius of the wafer in a direction from the edge of the one surface toward the center thereof and the central area of the one surface is defined as an area at 9.4% of the radius of the wafer from the center of the one surface.
    Type: Application
    Filed: January 14, 2021
    Publication date: September 2, 2021
    Applicant: SKC Co., Ltd.
    Inventors: Jong Hwi PARK, Sang Ki KO, Kap-Ryeol KU, Jung-Gyu KIM, Eun Su YANG, Yeon Sik LEE
  • Publication number: 20210123843
    Abstract: A method for preparing a SiC ingot includes: disposing a raw material and a SiC seed crystal facing each other in a reactor having an internal space; subliming the raw material by controlling a temperature, a pressure, and an atmosphere of the internal space; growing the SiC ingot on the seed crystal; and collecting the SiC ingot after cooling the reactor. The wafer prepared from the ingot, which is prepared from the method, generates cracks when an impact is applied to a surface of the wafer, the impact is applied by an external impact source having mechanical energy, and a minimum value of the mechanical energy is 0.194 J to 0.475 J per unit area (cm2).
    Type: Application
    Filed: June 29, 2020
    Publication date: April 29, 2021
    Applicant: SKC Co., Ltd.
    Inventors: Jong Hwi PARK, Jongmin SHIM, Eun Su YANG, Yeon Sik LEE, Byung Kyu JANG, Jung Woo CHOI, Sang Ki KO, Kap-Ryeol KU, Jung-Gyu KIM