Abstract: A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.

Abstract: A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.

Abstract: Provided is a pulse width modulation (PWM) pulse generating circuit, a device including the circuit, and a PWM control method. The circuit includes a detector to detect the frequency of the PWM clock signal and output a frequency detection signal including whether the frequency of the PWM clock signal is higher than a reference frequency, and a PWM pulse signal output unit to generate a PWM pulse signal according to a data signal, the PWM clock signal, and the frequency detection signal. When the frequency detection signal includes that the frequency of the PWM clock signal is higher than the reference frequency, the PWM pulse signal output unit generates the PWM pulse signal having a predetermined allowable pulse width or a pulse with that is higher than the predetermined allowable pulse width.

Abstract: A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.

Abstract: A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.

Abstract: A liquid crystal display (LCD) includes an LCD panel having a plurality of rows of pixel elements therein and a corresponding plurality of gate lines coupled to the plurality of rows of pixel elements. A gate line driver is also provided. The gate line driver is electrically coupled to the plurality of gate lines by a corresponding plurality of fan-out lines having unequal lengths and unequal resistance values. The gate line driver includes at least first and second buffers coupled to first and second ones of the plurality of fan-out lines, respectively. The first and second buffers having unequal pull-up impedances that inversely compensate for the unequal resistance values of the first and second ones of the plurality of fan-out lines.