Abstract: The present invention relates to an active material analysis apparatus for analyzing an active material of a battery. An active material analysis apparatus of the present invention may comprise: a lower plate at which an electrode is located; an upper plate which is coupled to the lower plate with the electrode disposed therebetween; a sealing member positioned at a joint part between the upper plate and the lower plate; and a coupling member for coupling the upper plate and the lower plate, wherein: the upper plate includes an opening provided to allow a light source to be radiated to the electrode; an electrolyte is filled in a space between the upper plate and the lower plate; the opening is covered by glass; and the upper plate faces a liquid surface formed by the electrolyte and is positioned at a position higher than that of the liquid surface.

Abstract: The present invention relates to an active material analysis apparatus for analyzing an active material of a battery. An active material analysis apparatus of the present invention may comprise: a lower plate at which an electrode is located; an upper plate which is coupled to the lower plate with the electrode disposed therebetween; a sealing member positioned at a joint part between the upper plate and the lower plate; and a coupling member for coupling the upper plate and the lower plate, wherein: the upper plate includes an opening provided to allow a light source to be radiated to the electrode; an electrolyte is filled in a space between the upper plate and the lower plate; the opening is covered by glass; and the upper plate faces a liquid surface formed by the electrolyte and is positioned at a position higher than that of the liquid surface.

Abstract: Provided is a method of increasing corrosion resistance of a magnesium (Mg) member. The method includes preparing a Mg member, and ion-implanting a doping element into a surface of the Mg member. Herein, the doping element includes an element capable of increasing a Fermi energy level of magnesium oxide (MgO) when doped on MgO.

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract: A semiconductor memory device and method of manufacturing the same are disclosed. The semiconductor memory device includes a semiconductor substrate having a cell region and a peripheral circuit region, first transistors provided on the semiconductor substrate, a first semiconductor layer provided on the first transistors, and bonded by a bonding technique, and second transistors provided on the first semiconductor layer, wherein the first and second transistors are provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer, respectively, and a metal layer is formed on gates of the first and second transistors respectively provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer. As a result, the transistors in the peripheral circuit region requiring high performance can be formed on an upper layer and a lower layer.

Abstract: An exposure apparatus includes a frame member with a first stage having a substrate disposed thereon provided in a lower portion of the frame member. A leveling mechanism is provided for adjusting an orientation of the first stage. The exposure apparatus further includes a second stage positioned over the first stage and fixed to the frame member. A reticle is positioned on the second stage. An exposure area limiting mechanism is provided in the exposure apparatus and positioned over the second stage. The exposure area limiting mechanism defines an opening through which light is capable of passing during exposure for limiting an exposure area of the second stage. The exposure apparatus also includes an illumination system to irradiate light to the exposure area limiting means.

Abstract: A light-exposing device for making a semiconductor device. A reticle has patterns to be exposed to light. A blind controls a light-exposing area of the reticle. An optical system between the blind and the reticle condenses light passing through the blind. Adjacent patterns on a reticle are consecutively projected by superimposing light-exposing energy. An extra optical system condenses light passing through the blind. The usable area of the reticle is maximized; the interval between patterns is not critical; and inferiority by either lack or excess of the exposure to light between the patterns is reduced.