Patents by Inventor Yeong-cheol Rhee

Yeong-cheol Rhee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8711076
    Abstract: A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ock Chul Shin, Yeong Cheol Rhee, Byung Koan Kim
  • Patent number: 8347000
    Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-koan Kim, Woo-chae Jeon, Jong-hoon Hong, Yeong-cheol Rhee, Ock-chul Shin
  • Publication number: 20110302340
    Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 8, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-koan KIM, Woo-chae JEON, Jong-hoon HONG, Yeong-cheol RHEE, Ock-chul SHIN
  • Publication number: 20100085368
    Abstract: A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.
    Type: Application
    Filed: October 6, 2009
    Publication date: April 8, 2010
    Inventors: Ock Chul SHIN, Yeong Cheol Rhee, Byung Koan Kim