Patents by Inventor Yeong-Chian Hu

Yeong-Chian Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7099321
    Abstract: A symmetric dual-slot data hash method and a switching apparatus using the same having a first block and a second block of equal size for storing MAC addresses. The size of the dual-slot address table is p×2m with m is an integer, and p is 2 or a prime. The hash address comprises a higher address portion and a lower address portion. A CRC hash operation is performed to the MAC address by using the m-bit CRC function to obtain a hash value. Next, the highest bit of the hash value is removed and the remained bits are used as the lower address portion of the hash address. A dividend is set according to the m-th bit of the MAC address. After the dividend is divided by a divisor p to obtain a remainder, the remainder is set as a higher address portion of the hash address.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: August 29, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Yeong-Chian Hu, Wei-Pin Chen
  • Patent number: 6697923
    Abstract: A method for buffer management and a controller of the same are disclosed. In the buffer management method, a first control mode is performed, and a plurality of bits are used to control a bit mask region of a memory. A second control mode is performed, and a plurality of unused addresses in a link region of the memory is cached. A third control mode is performed, to control a plurality of second unused addresses in the link region by a linked list. The controller comprises a plurality of bits for controlling a bit mask region; a plurality of address cache units for caching a plurality of first unused address of a linked list in a link region; and a pointer for always pointing to a head of the linked list in the link region, wherein the linked list links a plurality of second unused addresses.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: February 24, 2004
    Assignee: Via Technologies Inc.
    Inventors: Jen-Kai Chen, ChaoCheng Cheng, Yeong-Chian Hu
  • Publication number: 20040001506
    Abstract: An Ethernet switch controller with console command logic unit and application apparatus thereof implemented with the least cost. The switch controller includes a serial port interface that connects with an external ASCII console. A user can input a serial character command through this console. The switch controller interprets and executes the command it received. When the command is a read command, the controller sends the result to be displayed on the console. Therefore, advance function commands can be implemented for the Ethernet switch to read data from or write data to a register within the Ethernet switch controller, a physical layer or an EEPROM.
    Type: Application
    Filed: December 26, 2002
    Publication date: January 1, 2004
    Inventors: Jen-Kai Chen, Yeong-Chian Hu
  • Publication number: 20030093629
    Abstract: A method for buffer management and a controller of the same are disclosed. In the buffer management method, a first control mode is performed, and a plurality of bits are used to control a bit mask region of a memory. A second control mode is performed, and a plurality of unused addresses in a link region of the memory is cached. A third control mode is performed, to control a plurality of second unused addresses in the link region by a linked list. The controller comprises a plurality of bits for controlling a bit mask region; a plurality of address cache units for caching a plurality of first unused address of a linked list in a link region; and a pointer for always pointing to a head of the linked list in the link region, wherein the linked list links a plurality of second unused addresses.
    Type: Application
    Filed: November 15, 2001
    Publication date: May 15, 2003
    Inventors: Jen-Kai Chen, ChaoCheng Cheng, Yeong-Chian Hu
  • Publication number: 20020163919
    Abstract: A symmetric dual-slot data hash method and a switching apparatus using the same having a first block and a second block of equal size for storing MAC addresses. The size of the dual-slot address table is p×2m with m is an integer, and p is 2 or a prime. The hash address comprises a higher address portion and a lower address portion. A CRC hash operation is performed to the MAC address by using the m-bit CRC function to obtain a hash value. Next, the highest bit of the hash value is removed and the remained bits are used as the lower address portion of the hash address. A dividend is set according to the m-th bit of the MAC address. After the dividend is divided by a divisor p to obtain a remainder, the remainder is set as a higher address portion of the hash address.
    Type: Application
    Filed: April 29, 2002
    Publication date: November 7, 2002
    Inventors: Yeong-Chian Hu, Wei-Pin Chen