Abstract: A button-type secondary battery includes a lower can having a bottom surface; an upper can having a top, the upper can and the lower can being coupled to define a space therein; an electrolyte in the space; an electrode assembly in the space and including a negative electrode, a separator, and a positive electrode wound together; a gasket between the upper can and the lower can to electrically insulate the upper and lower cans; a top insulator that is electrically insulating and covering a top surface of the electrode assembly; and a bottom insulator that is electrically insulating and covering a bottom surface of the electrode assembly. The top and bottom insulators are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one of the top insulator and the bottom insulator are coated with a protective layer to prevent thermal shrinkage from occurring.

Abstract: A button type secondary battery includes a wound electrode assembly; a lower can with the electrode assembly and an electrolyte in the lower can; a top plate to close the lower can; a positive electrode terminal coupled to the top plate through a gasket to be electrically insulated from the top plate with a portion of the positive electrode terminal passing through a hole in the top plate to be bonded to a positive electrode tab; a top insulator covering a top surface of the electrode assembly; and a bottom insulator covering a bottom surface of the electrode assembly. The top insulator and the bottom insulator are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one or more of the top insulator and the bottom insulator are coated with a protective layer configured to prevent thermal shrinkage from occurring.

Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.

Abstract: A display device includes a first thin film transistor disposed on a substrate. A first insulating interlayer covers the first thin film transistor. An active pattern is disposed on the first insulating interlayer. The active pattern includes indium-gallium-zinc oxide (IGZO) having a thickness in a range of about 150 ? to about 400 ?. A gate insulation layer covers the active pattern. A gate pattern is disposed on the gate insulation layer. A second insulating interlayer covers the gate pattern.

Abstract: A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.

Abstract: A display device includes a polycrystalline semiconductor including a channel, a first electrode, and a second electrode of a driving transistor, a first gate insulating layer, a gate electrode of a driving transistor, a first electrode of a boost capacitor, a second gate insulating layer, a first interlayer insulating layer, an oxide semiconductor including a channel, a first electrode, and a second electrode of a second transistor, a channel, a first electrode, and a second electrode of a third transistor, and a second electrode of a boost capacitor, a third gate insulating layer disposed on the oxide semiconductor, a gate electrode of the second transistor overlapping the channel of the second transistor, a gate electrode of the third transistor overlapping the channel of the third transistor, and a second interlayer insulating layer disposed on the gate electrode of the second transistor and the gate electrode of the third transistor.

Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.

Abstract: A display device includes a first thin film transistor disposed on a substrate. A first insulating interlayer covers lire first thin film transistor. An active pattern is disposed on the first insulating interlayer. The active pattern includes indium-gallium-zinc oxide (IGZO) having a thickness in a range of about 150 ? to about 400 ?. A gate insulation layer covers the active pattern A gate pattern is disposed on the gate insulation layer. A second insulating interlayer covers the gate pattern.

Abstract: A display device includes a polycrystalline semiconductor including a channel, a first electrode, and a second electrode of a driving transistor, a first gate insulating layer, a gate electrode of a driving transistor, a first electrode of a boost capacitor, a second gate insulating layer, a first interlayer insulating layer, an oxide semiconductor including a channel, a first electrode, and a second electrode of a second transistor, a channel, a first electrode, and a second electrode of a third transistor, and a second electrode of a boost capacitor, a third gate insulating layer disposed on the oxide semiconductor, a gate electrode of the second transistor overlapping the channel of the second transistor, a gate electrode of the third transistor overlapping the channel of the third transistor, and a second interlayer insulating layer disposed on the gate electrode of the second transistor and the gate electrode of the third transistor.

Abstract: Provided are an oxide semiconductor device and a method for manufacturing same, wherein the oxide semiconductor device according to an embodiment of the inventive concept includes a substrate, and an oxide semiconductor layer on the substrate having different concentration of oxygen vacancy in the thickness direction.

Abstract: Provided are an oxide semiconductor device and a method for manufacturing same, wherein the oxide semiconductor device according to an embodiment of the inventive concept includes a substrate, and an oxide semiconductor layer on the substrate having different concentration of oxygen vacancy in the thickness direction.