Patents by Inventor Yeong Han GWON

Yeong Han GWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11462537
    Abstract: A semiconductor device includes a substrate, a first lower pattern and a second lower pattern on the substrate and arranged in a line in a first direction, a first active pattern stack disposed on and spaced apart from the first lower pattern, a second active pattern stack disposed on and spaced apart from the first lower pattern, a fin-cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern, a first gate structure surrounding the first active pattern stack and extending in a second direction crossing the first direction, a second gate structure surrounding the second active pattern stack and extending in the second direction, and a device isolation layer between the first gate structure and the second gate structure and separating the first lower pattern and the second lower pattern.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong Han Gwon, Soo Yeon Jeong, Geum Jong Bae, Dong Il Bae
  • Publication number: 20210035976
    Abstract: A semiconductor device includes a substrate, a first lower pattern and a second lower pattern on the substrate and arranged in a line in a first direction, a first active pattern stack disposed on and spaced apart from the first lower pattern, a second active pattern stack disposed on and spaced apart from the first lower pattern, a fin-cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern, a first gate structure surrounding the first active pattern stack and extending in a second direction crossing the first direction, a second gate structure surrounding the second active pattern stack and extending in the second direction, and a device isolation layer between the first gate structure and the second gate structure and separating the first lower pattern and the second lower pattern.
    Type: Application
    Filed: July 2, 2020
    Publication date: February 4, 2021
    Inventors: Yeong Han GWON, Soo Yeon JEONG, Geum Jong BAE, Dong Il BAE