Patents by Inventor Yeong Hwang

Yeong Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11998901
    Abstract: The present invention relates to a novel metal complex, a method for producing same, and a method for producing a gamma-lactam compound using same, and the metal complex according to the present invention is used as a catalyst for producing a gamma-lactam compound and can efficiently produce a gamma-lactam compound with an excellent yield and excellent selectivity.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: June 4, 2024
    Assignees: INSTITUTE FOR BASIC SCIENCE, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sukbok Chang, Seung Youn Hong, Yoon Su Park, Yeongyu Hwang, Yeong Bum Kim
  • Patent number: 11967267
    Abstract: Provided is a display device including a display panel, an optical sensor, a timing controller, a scan driver, a data driver, and an image controller. The timing controller controls an image refresh rate of the display panel based on a refresh rate control signal. Thus, the display device provides improved visibility.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: April 23, 2024
    Assignees: Samsung Display Co., Ltd., UNIST (Ulsan National Institute Of Science and Technology)
    Inventors: Hyo Sun Kim, Oh Sang Kwon, Seong Gyu Choe, Chang Yeong Han, Min Kyung Kim, You Ra Kim, Eun Jung Lee, Hyung Suk Hwang
  • Patent number: 11957476
    Abstract: Disclosed is a method of identifying dementia by at least one processor of a device. The method includes performing a first task that causes a first object to be displayed on a first region of a screen displayed on a user terminal; and when a preset condition is satisfied, performing a second task that causes at least one object, which induces the user's gaze, to be displayed instead of the first object on the screen of the user terminal.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: April 16, 2024
    Assignee: HAII CO, LTD.
    Inventors: Ho Yung Kim, Bo Hee Kim, Dong Han Kim, Hye Bin Hwang, Chan Yeong Park, Ji An Choi
  • Publication number: 20240081722
    Abstract: A method of identifying dementia is disclosed that includes causing a user terminal to display an N-th screen including a plurality of objects. The user terminal may further display an N+1-th screen with the objects rearranged at positions on the N+1-th screen which are different from positions of the objects included in the N-th screen when an N-th selection input of selecting any one from among the objects included in the N-th screen is received. When an N+1-th selection input for selecting any one from among the objects included in the N+1-th screen is received, a third task of determining whether an answer of the N+1-th selection input is correct is performed based on whether the object selected from the N+1-th selection input is the same as at least one object selected from at least one previous selection input including the N-th selection input.
    Type: Application
    Filed: July 7, 2022
    Publication date: March 14, 2024
    Applicant: HAII corp.
    Inventors: Ho Yung KIM, Geon Ha KIM, Bo Hee KIM, Dong Han KIM, Hye Bin HWANG, Chan Yeong PARK, Ji An CHOI, Bo Ri KIM
  • Patent number: 11913117
    Abstract: Disclosed is a hot-stamping component, which includes a base steel plate; and a plated layer on the base steel plate and including a first layer, a second layer, and an intermetallic compound portion having an island shape in the second layer, wherein the first layer and the second layer are sequentially stacked, and an area fraction of the intermetallic compound portion with respect to the second layer is an amount of 20% to 60%.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: February 27, 2024
    Assignee: Hyundai Steel Company
    Inventors: Hye Jin Kim, Kyu Yeon Hwang, Hyun Yeong Jung, Jin Ho Lee, Seung Pill Jung
  • Publication number: 20230125659
    Abstract: The present invention provides a hot stamping component having a tensile strength of 1350 Mpa or greater, including a microstructure including prior austenite grains (PAG), wherein an average particle diameter of the PAGs is 35 ?m or less.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 27, 2023
    Inventors: Hye Jin Kim, Jin Ho Lee, Je Youl Kong, Seung Chae Yoon, Seung Pill Jung, Hyun Yeong Jung, Kyu Yeong Hwang
  • Patent number: 11490162
    Abstract: A method for providing contents includes receiving a selection request for specific contents, from an electronic device; and providing, to the electronic device, an episode list of a plurality of episodes which constitute the specific contents, based on the selection request for the specific contents.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 1, 2022
    Assignee: NAVER WEBTOON LTD.
    Inventors: Ji Hoon Roh, Jeong Eun Yoon, Ellie Jieun Park, Jin Su Jang, Seon Yeong Hwang, Yong Soo Lee, Chang Min Jeon, Jun Kyu Park
  • Publication number: 20220192638
    Abstract: A method for analyzing an ultrasound image in the first trimester of pregnancy includes: acquiring an ultrasound image in the first trimester of pregnancy; and acquiring at least one of characteristics of uterus, fetus, placenta, gestational sac, and egg yolk related to the acquired ultrasound image, and determining a group pertinent to the acquired ultrasound image among a plurality of predesignated groups based on the acquired characteristic and the acquired ultrasound image, using an ultrasound image analysis device that has learned in a machine learning technique.
    Type: Application
    Filed: April 8, 2020
    Publication date: June 23, 2022
    Applicants: UNIVERSITY OF ULSAN FOUNDATION FOR INDUSTRY COOPERATION, THE ASAN FOUNDATION
    Inventors: Chong Jai KIM, Eun Na KIM, Joong Yeup LEE, Do Yeong HWANG, Ki Chul KIM, Jinyoung MA
  • Publication number: 20220038784
    Abstract: A method for providing contents includes receiving a selection request for specific contents, from an electronic device; and providing, to the electronic device, an episode list of a plurality of episodes which constitute the specific contents, based on the selection request for the specific contents.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 3, 2022
    Inventors: Ji Hoon ROH, Jeong Eun YOON, Ellie Jieun PARK, Jin Su JANG, Seon Yeong HWANG, Yong Soo LEE, Chang Min JEON, Jun Kyu PARK
  • Patent number: 11152390
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Patent number: 11004864
    Abstract: A semiconductor device includes a stack structure including alternately stacked interlayer insulating layers and electrode patterns. The semiconductor device also includes a plurality of contact plugs connected to the electrode patterns. The semiconductor device further includes a supporting structure penetrating the stack structure between two adjacent contact plugs of the plurality of contact plugs, wherein the supporting structure has a cross section extending in a zigzag shape.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyeok Jun Choi, Jun Yeong Hwang
  • Patent number: 10793671
    Abstract: Provided is an aliphatic polycarbonate macropolyol including —OAO— and Z(O—)a as repeating units. In the aliphatic polycarbonate macropolyol, the repeating units —OAO— and Z(O—)a are linked to each other via carbonyl (—C(O)—) linkers or are bonded to hydrogen to form terminal —OH groups. The number of moles of the terminal —OH groups is from aZ to aZ+0.2Z (where Z represents the number of moles of the repeating unit Z(O—)a). Further provided is an aliphatic polycarbonate-co-aromatic polyester macropolyol including —OAO— and Z(O—)a as repeating units. In the aliphatic polycarbonate-co-aromatic polyester macropolyol, the repeating units —OAO— and Z(O—)a are linked via carbonyl (—C(O)—) and —C(O)YC(O)— as linkers or are bonded to hydrogen to form terminal —OH groups.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: October 6, 2020
    Assignee: LOTTE CHEMICAL CORPORATION
    Inventors: Bun Yeoul Lee, Jong Yeob Jeon, Ji Hae Park, Jung Jae Lee, Eun Yeong Hwang
  • Publication number: 20200312878
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-il CHANG, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Publication number: 20200258901
    Abstract: A semiconductor device includes a stack structure including alternately stacked interlayer insulating layers and electrode patterns. The semiconductor device also includes a plurality of contact plugs connected to the electrode patterns. The semiconductor device further includes a supporting structure penetrating the stack structure between two adjacent contact plugs of the plurality of contact plugs, wherein the supporting structure has a cross section extending in a zigzag shape.
    Type: Application
    Filed: September 4, 2019
    Publication date: August 13, 2020
    Applicant: SK hynix Inc.
    Inventors: Hyeok Jun CHOI, Jun Yeong HWANG
  • Patent number: 10700092
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Publication number: 20190296047
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-il CHANG, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
  • Patent number: 10367002
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Patent number: 10160775
    Abstract: The present invention relates to a novel group 4 transition metal compound, a method for preparing the compound, a catalyst composition containing the compound, and a method for preparing a polyolefin, comprising a step for forming a polymerization reaction of olefin monomers in the presence of the catalyst composition. The group 4 transition metal compound of the present invention exhibits an excellent catalytic activity and has excellent thermal stability in a polyolefin synthesis reaction, and thus can be used even in a polyolefin synthesis reaction at a high temperature. In addition, the compound of the present invention can be advantageously used in the synthesis process of grade-controlled polyolefin since the weight average molecular weight of the synthesized polyolefin and the octane content in the polymer can be adjusted by varying the kinds of center metal and ligand.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 25, 2018
    Assignee: HANWHA CHEMICAL CORPORATION
    Inventors: Ui Gab Joung, Dong Ok Kim, Dong Wook Kim, Ah Reum Kim, Hye Ran Park, Kil Sagong, Sung Hae Jun, Chun Sun Lee, Eun Yeong Hwang
  • Publication number: 20180186929
    Abstract: Provided is an aliphatic polycarbonate macropolyol including —OAO— and Z(O—)a as repeating units. In the aliphatic polycarbonate macropolyol, the repeating units —OAO— and Z(O—)a are linked to each other via carbonyl (—C(O)—) linkers or are bonded to hydrogen to form terminal —OH groups. The number of moles of the terminal —OH groups is from aZ to aZ+0.2 Z (where Z represents the number of moles of the repeating unit Z(O—)a). Further provided is an aliphatic polycarbonate-co-aromatic polyester macropolyol including —OAO— and Z(O—)a as repeating units. In the aliphatic polycarbonate-co-aromatic polyester macropolyol, the repeating units —OAO— and Z(O—)a are linked via carbonyl (—C(O)—) and —C(O)YC(O)— as linkers or are bonded to hydrogen to form terminal —OH groups.
    Type: Application
    Filed: February 8, 2018
    Publication date: July 5, 2018
    Inventors: Bun Yeoul Lee, Jong Yeob Jeon, Ji Hae Park, Jung Jae Lee, Eun Yeong Hwang
  • Publication number: 20180179333
    Abstract: Provided is an aliphatic polycarbonate macropolyol including —OAO— and Z(O—)a as repeating units. In the aliphatic polycarbonate macropolyol, the repeating units —OAO— and Z(O—)a are linked to each other via carbonyl (—C(O)—) linkers or are bonded to hydrogen to form terminal —OH groups. The number of moles of the terminal —OH groups is from aZ to aZ+0.2Z (where Z represents the number of moles of the repeating unit Z(O—)a). Further provided is an aliphatic polycarbonate-co-aromatic polyester macropolyol including —OAO— and Z(O—)a as repeating units. In the aliphatic polycarbonate-co-aromatic polyester macropolyol, the repeating units —OAO— and Z(O—)a are linked via carbonyl (—C(O)—) and —C(O)YC(O)— as linkers or are bonded to hydrogen to form terminal —OH groups.
    Type: Application
    Filed: February 8, 2018
    Publication date: June 28, 2018
    Inventors: Bun Yeoul Lee, Jong Yeob Jeon, Ji Hae Park, Jung Jae Lee, Eun Yeong Hwang