Abstract: An electronic device, and more particularly, a page buffer is provided. The page buffer includes a sensing node configured to sense a potential of a bit line coupled to a memory cell, a precharging circuit coupled to the sensing node and configured to precharge a potential of the sensing node to a first voltage during an evaluation operation on the memory cell, a discharging circuit coupled to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage, and a latch circuit coupled to the discharging circuit and configured to store therein data sensed from the memory cell based on a result of comparing the potential of the sensing node with a reference voltage after the potential of the sensing node is discharged to the second voltage and a predetermined period elapses.

Abstract: A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Abstract: A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Abstract: A memory device including: a memory block including a word lines, word lines located in the middle of the word lines are used as dummy word lines, a control circuit establish word lines stacked on one side and other side of the dummy word lines into a first and second sub-blocks, respectively, performs an independent erase operation on one of the first and second sub-blocks in an erase operation period, and a control logic differently sets a level of a first transfer voltage for controlling transfer of an erase common voltage to the selected sub-block and the level of a second transfer voltage for controlling transfer of the erase common voltage to the unselected sub-block, applies an erase allowable voltage from the erase common voltage to a word line of the selected sub-block, and floats a word line of the unselected sub-block, in the erase operation period.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.

Abstract: A memory device comprising: a plurality of memory blocks each including a plurality of word lines arranged between a first and second select line, a peripheral circuit performs an erase operation by applying an erase voltage to a source or drain line of a selected memory block, and a control logic controls, in a period in which the erase operation is performed, the peripheral circuit to: sequentially select the plurality of word lines included in the selected memory block at least one by one from a word line closest to the first and second select line to a word line farthest from the first and second select line, apply a first erase permission voltage to the selected word lines, and apply a second erase permission voltage, which have a higher potential level than the first erase permission voltage, to remaining word lines except the selected word lines.

Abstract: A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N?1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

Abstract: A memory device and method of operation includes memory cells and a program operation performer configured to perform a verify operation and a program voltage apply operation, wherein the verify operation verifies whether threshold voltages of the memory cells have reached threshold voltages corresponding to a target program state using a first verify voltage, a second verify voltage higher than the first verify voltage and a third verify voltage higher than the second verify voltage, and the program voltage apply operation applies a program voltage to a word line. The memory device and method of operation also includes a program operation controller configured to control the program operation performer such that, during the program voltage apply operation, a precharge voltage is first applied to a second bit line coupled to a second memory cell before a precharge voltage is applied to a first bit line.

Abstract: An electronic device, and more particularly, a page buffer is provided. The page buffer includes a sensing node configured to sense a potential of a bit line coupled to a memory cell, a precharging circuit coupled to the sensing node and configured to precharge a potential of the sensing node to a first voltage during an evaluation operation on the memory cell, a discharging circuit coupled to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage, and a latch circuit coupled to the discharging circuit and configured to store therein data sensed from the memory cell based on a result of comparing the potential of the sensing node with a reference voltage after the potential of the sensing node is discharged to the second voltage and a predetermined period elapses.

Abstract: A nonvolatile memory device comprising: a cell string comprising a plurality of memory cells, a bit line coupled to the cell string, and a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period, wherein the page buffer comprises: a first coupling unit suitable for coupling the bit line and the first sensing node, a second coupling unit suitable for coupling the first and second sensing nodes, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period, a first and second latch units suitable for latching a logic levels corresponding to a voltage levels of the first and second sensing nodes, respectively.

Abstract: A memory device including: a memory block including a word lines, word lines located in the middle of the word lines are used as dummy word lines, a control circuit establish word lines stacked on one side and other side of the dummy word lines into a first and second sub-blocks, respectively, performs an independent erase operation on one of the first and second sub-blocks in an erase operation period, and a control logic differently sets a level of a first transfer voltage for controlling transfer of an erase common voltage to the selected sub-block and the level of a second transfer voltage for controlling transfer of the erase common voltage to the unselected sub-block, applies an erase allowable voltage from the erase common voltage to a word line of the selected sub-block, and floats a word line of the unselected sub-block, in the erase operation period.

Abstract: A nonvolatile memory device comprising: a cell string comprising a plurality of memory cells, a bit line coupled to the cell string, and a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period, wherein the page buffer comprises: a first coupling unit suitable for coupling the bit line and the first sensing node, a second coupling unit suitable for coupling the first and second sensing nodes, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period, a first and second latch units suitable for latching a logic levels corresponding to a voltage levels of the first and second sensing nodes, respectively.

Abstract: A memory device comprising: a plurality of memory blocks each including a plurality of word lines arranged between a first and second select line, a peripheral circuit performs an erase operation by applying an erase voltage to a source or drain line of a selected memory block, and a control logic controls, in a period in which the erase operation is performed, the peripheral circuit to: sequentially select the plurality of word lines included in the selected memory block at least one by one from a word line closest to the first and second select line to a word line farthest from the first and second select line, apply a first erase permission voltage to the selected word lines, and apply a second erase permission voltage, which have a higher potential level than the first erase permission voltage, to remaining word lines except the selected word lines.

Abstract: An electronic device is provided. A memory device controls a signal for setting a voltage level of a bit line. The memory device includes a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops for programming selected memory cells among the plurality of memory cells, and a sense signal controller configured to determine, during a program operation on a first memory cell among the selected memory cells, a bit line set-up time of a bit line coupled to the first memory cell based on at least one of a state of second memory cells adjacent to the first memory cell and a number of program loops performed on the first memory cell, the first memory cell having a threshold voltage higher than a pre-verify voltage and lower than a main verify voltage.

Abstract: A three-dimensional semiconductor device is provided. The three-dimensional device may include substrate; a common electrode layer on the substrate; a word line stack disposed on the common electrode layer, the word line stack having interlayer insulating layers and word lines structures alternately stacked and; and a vertical channel pillar penetrating the word line stack, the vertical channel pillar being electrically connected to the common electrode layer. Each of the word line structures includes a body portion having a first vertical width and an extension portion having a second vertical width greater than the first vertical width. The extension portion abuts the vertical channel pillar.

Abstract: A memory device that controls a floating time point of word lines connected to a sub block adjacent to a sub block on which an erase operation is performed includes a plurality of memory blocks each including a plurality of sub blocks, a voltage generator configured to generate a plurality of voltages to perform an erase operation on any of the plurality of sub blocks, and control logic configured to divide a plurality of word lines connected to an adjacent sub block neighboring a sub block on which the erase operation is performed into a plurality of groups, and configured to control the voltage generator to differently set a floating time point of word lines included in each group for each of the plurality of groups, during the erase operation.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.

Abstract: An electronic device is provided. A memory device controls a signal for setting a voltage level of a bit line. The memory device includes a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops for programming selected memory cells among the plurality of memory cells, and a sense signal controller configured to determine, during a program operation on a first memory cell among the selected memory cells, a bit line set-up time of a bit line coupled to the first memory cell based on at least one of a state of second memory cells adjacent to the first memory cell and a number of program loops performed on the first memory cell, the first memory cell having a threshold voltage higher than a pre-verify voltage and lower than a main verify voltage.

Abstract: A memory device that controls a floating time point of word lines connected to a sub block adjacent to a sub block on which an erase operation is performed includes a plurality of memory blocks each including a plurality of sub blocks, a voltage generator configured to generate a plurality of voltages to perform an erase operation on any of the plurality of sub blocks, and control logic configured to divide a plurality of word lines connected to an adjacent sub block neighboring a sub block on which the erase operation is performed into a plurality of groups, and configured to control the voltage generator to differently set a floating time point of word lines included in each group for each of the plurality of groups, during the erase operation.