Abstract: A three-dimensional semiconductor device is provided. The three-dimensional device may include substrate; a common electrode layer on the substrate; a word line stack disposed on the common electrode layer, the word line stack having interlayer insulating layers and word lines structures alternately stacked and; and a vertical channel pillar penetrating the word line stack, the vertical channel pillar being electrically connected to the common electrode layer. Each of the word line structures includes a body portion having a first vertical width and an extension portion having a second vertical width greater than the first vertical width. The extension portion abuts the vertical channel pillar.

Abstract: Disclosed is a semiconductor device including a plurality of strings connected between a plurality of bit lines and a source line, a plurality of page buffers connected to the plurality of bit lines, respectively, and configured to adjust a voltage level of each of the plurality of bit lines, and a control circuit configured to control the plurality of page buffers to fix a voltage level of a bit line connected to a string including a memory cell on which a program operation has been completely performed and to change a voltage level of a bit line connected to a string including a memory cell on which the program operation has not been completely performed, during a de-trap operation.

Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, a plurality of page buffers respectively coupled to the plurality of memory cells through bit lines, and a control logic configured to control a program operation of each of the plurality of page buffers. Each of the plurality of page buffers may include a first latch circuit configured to store first data indicating a main verification result obtained using a main verify voltage, a second latch circuit configured to store second data indicating a first sub-verification result obtained using a first sub-verify voltage lower than the main verify voltage, and a third latch circuit configured to store third data indicating a second sub-verification result obtained using a second sub-verify voltage lower than the first sub-verify voltage.

Abstract: The present technology relates to an electronic device. According to the present technology, a page buffer may include a bit line voltage control circuit, a latch and a reference voltage supply circuit. The bit line voltage control circuit may selectively connect a bit line and a sensing node. The latch may provide a latch signal corresponding to data. The reference voltage supply circuit may include a first PMOS transistor and a first NMOS transistor coupled in series between the sensing node and a ground voltage terminal, and apply a first reference voltage to the sensing node. The first PMOS transistor may be controlled according to the reference voltage control signal. The first NMOS transistor may be controlled by the latch signal.

Abstract: A memory device includes: a memory block including a plurality of memory cells; a peripheral circuit for performing a program operation on selected memory cells among the plurality of memory cells; and a control logic for controlling the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a foggy program operation on first memory cells connected to a first word line among the plurality of memory cells, perform a foggy program operation on second memory cells connected to a second word line adjacent to the first word line among the plurality of memory cells, and perform a fine program operation on the first memory cells, based on a target program state of the second memory cells.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers each performing an auxiliary verify operation and a main verify operation, which are used to program selected memory cells among the plurality of memory cells; and control logic for controlling the auxiliary verify operation and the main verify operation of the peripheral circuit. During the main verify operation, the control logic controls the peripheral circuit to selectively precharge sensing nodes of the plurality page buffers respectively corresponding to the selected memory cells, based on a result of the auxiliary verify operation.

Abstract: A memory device includes: a memory cell array including a cell string including a plurality of memory cells respectively connected between a common source line and a plurality of bit lines; a peripheral circuit for performing an internal operation on the memory cells; and control logic for controlling the peripheral circuit to apply a voltage necessary for the internal operation to word lines connected to the plurality of memory cells. The peripheral circuit includes a pass voltage information generator for generating pass voltage information including a number of clocks input from a time at which a pass voltage is applied to the word lines to a time at which a voltage level of the common source line reaches a predetermined reference level. The control logic includes a pass voltage determiner for determining a pass voltage to be applied to the word lines, based on the pass voltage information.

Abstract: A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N?1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

Abstract: Provided herein may be a semiconductor memory and a method of operating the same. By the method, at least one normal program loop may be performed on a first memory cell, among a plurality of memory cells included in a page selected as a program target, having an N-th program state, among a plurality of program states, as a target program state, and at least one blind program loop may be performed on the first memory cell. While the at least one blind program loop is being performed, a target data pattern that is stored in a data latch of a first page buffer coupled to the first memory cell and that corresponds to the N-th program state may be changed to a first data pattern corresponding to a first program state that is lower than the N-th program state, and wherein N is a natural number equal to or greater than 2.

Abstract: A memory device, and a method of operating the memory device, includes a memory block, a peripheral circuit, an erase controller, and a parameter setter. The memory device includes a plurality of sub blocks. The peripheral circuit performs an erase operation on a target sub block among the plurality of sub blocks. The erase controller controls the peripheral circuit to perform the erase operation based on a default parameter or an optimal parameter according to a group to which the target sub block belongs among first, second, and third groups. The parameter setter sets the optimal parameter based on a result of the erase operation when the target sub block is included in the first group or the third group.

Abstract: A memory device and method of operation includes memory cells and a program operation performer configured to perform a verify operation and a program voltage apply operation, wherein the verify operation verifies whether threshold voltages of the memory cells have reached threshold voltages corresponding to a target program state using a first verify voltage, a second verify voltage higher than the first verify voltage and a third verify voltage higher than the second verify voltage, and the program voltage apply operation applies a program voltage to a word line. The memory device and method of operation also includes a program operation controller configured to control the program operation performer such that, during the program voltage apply operation, a precharge voltage is first applied to a second bit line coupled to a second memory cell before a precharge voltage is applied to a first bit line.

Abstract: A memory device includes a memory cell array including a first memory cell connected to a first channel structure, and a second memory cell connected to a second channel structure; a peripheral circuit for performing a program operation of storing data in the first and second memory cells commonly connected to a word line; and a program operation controller for controlling the peripheral circuit to perform the program operation, the program operation including an intermediate program operation performed on the first memory cell and then on the second memory cell, and a final program operation preformed to have a threshold voltage of the first and second memory cells to a threshold voltage corresponding to a target program state.

Abstract: Provided herein is a memory device for performing a foggy-fine program operation and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells, a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of cells, and a control logic configured to control the program operation by the peripheral circuit. The control logic is configured to control the peripheral circuit to perform a foggy program operation on first memory cells coupled to a first word line, among the plurality of memory cells, perform a foggy program operation on second memory cells coupled to a second word line adjacent to the first word line, among the memory cells, and perform a fine program operation on the first memory cells by decreasing a verify pass voltage to be applied to the second word line.

Abstract: A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N?1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

Abstract: An electronic device, and more particularly, a page buffer is provided. The page buffer includes a sensing node configured to sense a potential of a bit line coupled to a memory cell, a precharging circuit coupled to the sensing node and configured to precharge a potential of the sensing node to a first voltage during an evaluation operation on the memory cell, a discharging circuit coupled to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage, and a latch circuit coupled to the discharging circuit and configured to store therein data sensed from the memory cell based on a result of comparing the potential of the sensing node with a reference voltage after the potential of the sensing node is discharged to the second voltage and a predetermined period elapses.

Abstract: A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Abstract: A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Abstract: A memory device including: a memory block including a word lines, word lines located in the middle of the word lines are used as dummy word lines, a control circuit establish word lines stacked on one side and other side of the dummy word lines into a first and second sub-blocks, respectively, performs an independent erase operation on one of the first and second sub-blocks in an erase operation period, and a control logic differently sets a level of a first transfer voltage for controlling transfer of an erase common voltage to the selected sub-block and the level of a second transfer voltage for controlling transfer of the erase common voltage to the unselected sub-block, applies an erase allowable voltage from the erase common voltage to a word line of the selected sub-block, and floats a word line of the unselected sub-block, in the erase operation period.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.

Abstract: A memory device comprising: a plurality of memory blocks each including a plurality of word lines arranged between a first and second select line, a peripheral circuit performs an erase operation by applying an erase voltage to a source or drain line of a selected memory block, and a control logic controls, in a period in which the erase operation is performed, the peripheral circuit to: sequentially select the plurality of word lines included in the selected memory block at least one by one from a word line closest to the first and second select line to a word line farthest from the first and second select line, apply a first erase permission voltage to the selected word lines, and apply a second erase permission voltage, which have a higher potential level than the first erase permission voltage, to remaining word lines except the selected word lines.