Abstract: A memory device that controls a floating time point of word lines connected to a sub block adjacent to a sub block on which an erase operation is performed includes a plurality of memory blocks each including a plurality of sub blocks, a voltage generator configured to generate a plurality of voltages to perform an erase operation on any of the plurality of sub blocks, and control logic configured to divide a plurality of word lines connected to an adjacent sub block neighboring a sub block on which the erase operation is performed into a plurality of groups, and configured to control the voltage generator to differently set a floating time point of word lines included in each group for each of the plurality of groups, during the erase operation.