Patents by Inventor Yeong-Jong Jeong

Yeong-Jong Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9972717
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Seo-Jin Jeong
  • Patent number: 9608054
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong
  • Publication number: 20160343859
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong JEONG, Jeong-Yun Lee, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Seo-Jin Jeong
  • Patent number: 9443852
    Abstract: Integrated circuit devices with source/drain regions including multiple segments and methods of forming the same are provided. The integrated circuit devices may include a gate structure on a substrate and a source/drain region in the substrate adjacent the gate structure. The source/drain region may include a sidewall including a plurality of curved sidewall sections.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Dong-Hyun Kim, Bok-Young Lee
  • Patent number: 9431478
    Abstract: A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Seo-Jin Jeong
  • Patent number: 9419072
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong
  • Publication number: 20160141381
    Abstract: Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern. The gate spacer includes first, second and third spacers that sequentially come in contact with each other in a direction in which the gate spacer goes out from the gate electrode, and a carbon concentration of the second spacer is lower than carbon concentrations of the first and third spacers.
    Type: Application
    Filed: August 3, 2015
    Publication date: May 19, 2016
    Inventors: Kook-Tae KIM, Ho-Sung Son, Geo-Myung Shin, Dong-Suk Shin, Si-Hyung Lee, Ji-Hye Yi, Sung-Hoon Jung, Yeong-Jong Jeong
  • Patent number: 9318575
    Abstract: A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Li Quan
  • Publication number: 20160056259
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Application
    Filed: November 5, 2015
    Publication date: February 25, 2016
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong
  • Patent number: 9263521
    Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Li Quan, Dong-Suk Shin, Si-Hyung Lee
  • Publication number: 20150318399
    Abstract: A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
    Type: Application
    Filed: January 20, 2015
    Publication date: November 5, 2015
    Inventors: Yeong-Jong JEONG, Jeong-Yun LEE, Geo-Myung SHIN, Dong-Suk SHIN, Si-Hyung LEE, Seo-Jin JEONG
  • Publication number: 20150249130
    Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.
    Type: Application
    Filed: May 15, 2015
    Publication date: September 3, 2015
    Inventors: Yeong-Jong JEONG, Jeong-Yun Lee, Shi Li Quan, Dong-Suk Shin, Si-Hyung Lee
  • Publication number: 20150236015
    Abstract: Integrated circuit devices with source/drain regions including multiple segments and methods of forming the same are provided. The integrated circuit devices may include a gate structure on a substrate and a source/drain region in the substrate adjacent the gate structure. The source/drain region may include a sidewall including a plurality of curved sidewall sections.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 20, 2015
    Inventors: Yeong-Jong JEONG, Jeong-Yun LEE, Dong-Hyun KIM, Bok-Young LEE
  • Publication number: 20150140759
    Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.
    Type: Application
    Filed: September 19, 2014
    Publication date: May 21, 2015
    Inventors: Yeong-Jong JEONG, Jeong-Yun Lee, Shi li Quan, Dong-Suk Shin, Si-Hyung Lee
  • Patent number: 9034700
    Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 19, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Ii Quan, Dong-Suk Shin, Si-Hyung Lee
  • Publication number: 20150132908
    Abstract: A semiconductor device and method of fabricating the device, includes forming a fin-type active pattern that projects above a field insulating layer and forming a dummy gate structure that includes an epitaxial growth prevention layer to suppress nodule formation.
    Type: Application
    Filed: June 3, 2014
    Publication date: May 14, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Ii Quan, Sug-Hyun Sung
  • Publication number: 20150126012
    Abstract: A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.
    Type: Application
    Filed: June 24, 2014
    Publication date: May 7, 2015
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Li Quan
  • Publication number: 20130270569
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Application
    Filed: June 11, 2013
    Publication date: October 17, 2013
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong
  • Patent number: 8466023
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong
  • Publication number: 20110092040
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Application
    Filed: August 30, 2010
    Publication date: April 21, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong