Patents by Inventor Yeong-jun Cho

Yeong-jun Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12283039
    Abstract: The present disclosure in some embodiments provides a product inspection method and a system based on deep learning for detecting a product defect. The present disclosure provides a product inspection method and system for detecting product defects by linking a predeveloped deep learning-based classification model to interwork with the existing product inspection system while fine-tuning the classification model to be maintained or supplemented by instantly correcting errors of the classification model, thereby improving the accuracy of product quality inspection.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: April 22, 2025
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventors: Tae Hyun Kim, Hye Rin Kim, Yeong Jun Cho
  • Publication number: 20220189002
    Abstract: The present disclosure in some embodiments provides a product inspection method and a system based on deep learning for detecting a product defect. The present disclosure provides a product inspection method and system for detecting product defects by linking a predeveloped deep learning-based classification model to interwork with the existing product inspection system while fine-tuning the classification model to be maintained or supplemented by instantly correcting errors of the classification model, thereby improving the accuracy of product quality inspection.
    Type: Application
    Filed: November 1, 2021
    Publication date: June 16, 2022
    Applicant: HYUNDAI MOBIS CO., LTD.
    Inventors: Tae Hyun KIM, Hye Rin KIM, Yeong Jun CHO
  • Publication number: 20110316119
    Abstract: Provided is a semiconductor package including a de-coupling capacitor. The semiconductor package includes a substrate, on an upper surface of which a semiconductor chip is mounted; a plurality of first conductive bumps that are disposed on a lower surface of the substrate and that electrically connect the substrate to an external device; and a de-coupling capacitor that is disposed on the lower surface of the substrate and includes an electrode portion and at least one dielectric layer, wherein the electrode portion of the de-coupling capacitor includes second conductive bumps that electrically connect the substrate to an external device.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 29, 2011
    Inventors: Yong-hoon KIM, Yeong-jun Cho, Ji-hyun Lee, Hee-seok Lee