Abstract: An architecture for performing the two-dimensional discrete wavelet transform includes a transform module including a first stage and a second stage for decomposing an input image into four bands, and among the four bands, the band having the low frequency in both horizontal and vertical direction serves as the input image for next level decomposition operation; a multiplexer for selecting the band having the low frequency in both horizontal and vertical direction as the input image to feed into the transform module; and an optional memory module for storing the band having the lowest frequency in both horizontal and vertical direction.

Abstract: A motion estimator, employing a three-step hierarchical search block-matching algorithm for obtaining a motion vector by block-matching between a current block and its corresponding block, is provided. The motion estimator comprises: a memory block, a matching unit and a control unit. The memory block is for storing a candidate block corresponding to the current block. The matching unit matches the size of a current block with aforementioned candidate block and sub-candidate blocks identical to the current block. The control unit supplies candidate blocks in the memory blocks to the matching unit according to a prescribed matching sequence, and writes the candidate block corresponding to the current block to the section no longer used in the memory block simultaneous to the performance of Step 3 of a three-step hierarchical search block-matching algorithm.

Abstract: The invention discloses a 9-cell array architecture with data-rings for 3-step hierarchical search (3SHS) block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator tree-like structure can be used to simply internal I/O controller and reduce latency. In addition, we can utilize techniques to reduce external memory accesses and interconnections. The results demonstrate that the array architecture with the data-rings is low in terms of latency, memory bandwidth and costs and a high performance solution for the 3 SHS.