Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.

Abstract: A polar code decoding apparatus and an operation method thereof are provided. The polar code decoding apparatus includes a path expanding circuit and a node processing circuit. The path expanding circuit expands each of multiple previous paths corresponding to multiple previous decoding results into multiple candidate paths according to a current node. The path expanding circuit dynamically determines a path expanding number of the candidate paths of each of the previous paths according to an unreliable information bit number of the current node. The node processing circuit performs a path competition operation to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results.

Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.

Abstract: A successive cancellation list-based decoder and a decoding method thereof are provided. In the method, an error check is performed on a set of data bits. A data unit includes the set of the data bits and at least one first check bit. Part of the set of data bits are considered as at least one second check bit. At each of the second check bits, its previous error-check result are verified, where the verified result is related to a comparison between each of the previous first check bits and a value obtained through a function calculation on corresponding data bits. The verified result at each of the second check bits determines whether to continue decoding of the set of data bits or to early terminate the decoding process. The method is able to increase the probability for early termination of the decoding process and to improve the decoding efficiency.

Abstract: A successive cancellation list-based decoder and a decoding method thereof are provided. In the method, an error check is performed on a set of data bits. A data unit includes the set of the data bits and at least one first check bit. Part of the set of data bits are considered as at least one second check bit. At each of the second check bits, its previous error-check result are verified, where the verified result is related to a comparison between each of the previous first check bits and a value obtained through a function calculation on corresponding data bits. The verified result at each of the second check bits determines whether to continue decoding of the set of data bits or to early terminate the decoding process. The method is able to increase the probability for early termination of the decoding process and to improve the decoding efficiency.

Abstract: The disclosure provides a non-orthogonal multiple access data transmission method and a transmission device using the same. The method includes: performing channel encoding for a plurality of data and a plurality of identifiers respectively corresponding to the plurality of data by using Raptor code so as to generate a Raptor codeword, wherein the plurality of identifiers respectively correspond to a plurality of receiving terminals; and modulating the Raptor codeword to generate a plurality of modulation symbols and broadcasting the plurality of modulation symbols.

Abstract: The disclosure provides a non-orthogonal multiple access data transmission method and a transmission device using the same. The method includes: performing channel encoding for a plurality of data and a plurality of identifiers respectively corresponding to the plurality of data by using Raptor code so as to generate a Raptor codeword, wherein the plurality of identifiers respectively correspond to a plurality of receiving terminals; and modulating the Raptor codeword to generate a plurality of modulation symbols and broadcasting the plurality of modulation symbols.

Abstract: An iterative decoding device applied for a SISO (soft input soft output) system is disclosed, which comprises an operational control unit, a first decoder, and a second decoder. The operational control unit is operative to receive an encoded signal and divide the encoded signal into at least one frame. The first decoder is operative to receive each of the at least one frame and derive a renewed intrinsic information by a first iteration operation. The second decoder is operative to derive soft-information by a second iteration operation based on the renewed intrinsic information, and then transmit the soft-information back to the first decoder for the iteration operation of the next renewed intrinsic information. The operational control unit makes the at least one frame to be calculated respectively by the first decoder and the second decoder, thereby improving the efficiency and error ratio of a receiver.

Abstract: A decoding method for low density parity check (LDPC) code, used to decode an input signal into a correct codeword according to a predetermined LDPC matrix, is provided. The method includes performing a plurality of decoding attempts according to the LDPC matrix within a predetermined number of decoding attempts, the plurality of decoding attempts at least including a first decoding attempt with use of a first decoding schedule and a second decoding attempt with use of a second decoding schedule. The second decoding attempt is adjacently subsequent to the first decoding attempt. The first decoding schedule as a group is not included in the second decoding schedule.

Abstract: An encoding and decoding method of low-density parity-check code is disclosed. The method is following steps: a high rate check code is transferred to a check matrix having a protograph. The check matrix is extended to form an extended base matrix and is split to form a split base matrix. The extended base matrix and the split base matrix are respectively calculated to generate their decoding threshold by a protograph extrinsic information transfer chart. The base matrix with the lower decoding threshold is considered as a low rate base matrix. Repeating the above process until a stop condition is satisfied. The last low rate base matrix is expanded to form a parity check matrix. The transmission data is encoded and decoded by the parity check matrix.

Abstract: An extreme index finder and a digital value finding method are provided. The extreme index finder includes a plurality of digital-to-time converters (DTCs) and a first arbiter apparatus. The DTCs respectively receive a plurality of input signals and perform a digital-to-time converting operation on each of the input signals to respectively generate a plurality of time-domain signals. The first arbiter apparatus finds a position of a extreme value in the time-domain signals according to transition speeds of the time-domain signals and compares transition speed of the extreme value with each of the time-domain signals to find an extreme input signal corresponding to the extreme value in the input signals.

Abstract: An iterative decoding device applied for a SISO (soft input soft output) system is disclosed, which comprises an operational control unit, a first decoder, and a second decoder. The operational control unit is operative to receive an encoded signal and divide the encoded signal into at least one frame. The first decoder is operative to receive each of the at least one frame and derive a renewed intrinsic information by a first iteration operation. The second decoder is operative to derive soft-information by a second iteration operation based on the renewed intrinsic information, and then transmit the soft-information back to the first decoder for the iteration operation of the next renewed intrinsic information. The operational control unit makes the at least one frame to be calculated respectively by the first decoder and the second decoder, thereby improving the efficiency and error ratio of a receiver.

Abstract: A decoding method of a LDPC comprises following steps. A first predetermined number of iterations of a messages-passing decoding algorithm are applied to a received signal vector, so as to attempt to decode a transmitted (or stored) codeword. Whether the decoding result converges to a valid codeword is determined by observing whether the decoding result makes all check nodes satisfied or not. When the decoding result does not converge to a valid codeword, the value of at least one of the variable nodes neighboring to one of the un-satisfied check node is be adjusted to a non-zero value, wherein the selected variable node is included in a trapping set. Then, a second predetermined number of iterations of the messages-passing decoding algorithm are applied to the updated decoding result to generate another one decoding result, and whether the other one decoding result converges to a valid codeword is checked.

Abstract: A method of finding a minimum and a minimum finder utilizing the same are provided. The method, adopted by the minimum finder, determining a minimum and a probabilistic second minimum from a plurality of inputs, includes: providing a plurality of Minimum-Value Generators (MVG) to form a binary tree, wherein each MVG receives two of the plurality of inputs, compares the values of the two inputs to output a comparison result; and receiving, by a minimum-and-second-minimum generator, the comparison results of two of the plurality of MVGs to generate the minimum and the probabilistic second minimum; wherein the minimum-and-second-minimum generator is not connected to a MVG in a top layer of the binary tree.

Abstract: An unequal bit-reliability information storage method for communication and storage systems at least includes one storage unit having a first memory and a second memory; the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory. Based on the significance of each bit of the information with the use of the first or second memories of different reliability for storage, the complexity of the storage unit, the production cost and the power consumption can be reduced while maintaining the performance.

Abstract: A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained.

Abstract: A system providing early termination for channel decoding by re-encoding including a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and to the encoding unit. Via the system, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding. Re-encoded words are compared to the decoded codewords by the checking unit and, if they are completely the same, the decoding action of the decoding unit is terminated. The system reduces power consumption and offers a simplified structure, improved decoding throughput, and reduced hardware complexity.

Abstract: A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained.

Abstract: The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.

Abstract: A method of early termination for channel decoding by re-encoding according to the invention at least includes a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and the encoding unit; by means of the configuration of the above units, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding; the re-encoded words are compared to the decoded codewords by the checking unit; and if they are completely the same, then terminate the decoding action of the decoding unit. It achieves saved power consumption, simplified structure, improved decoding throughput and less hardware complexity.