Abstract: A method for plasma etching a wafer after a backside grinding process which incorporates an oxidation pretreatment step is disclosed. The method includes the step of first grinding a backside of a wafer to expose a bare silicon surface. The bare silicon surface is then oxidized in an oxidation chamber to form a substantially uniform silicon oxide layer of at least 50 ? thick, and preferably at least 100 ? thick. The wafer is then positioned in a plasma etch chamber with an active surface of the wafer exposed, and a surface layer etched away by an oxygen plasma without causing any further silicon oxide formation on the backside of the wafer. The present invention novel plasma etching method can be advantageously used for removing an organic material layer, such as a photoresist layer from a wafer surface.

Abstract: A method of improving photoresist adhesion in a reworked device, including the following steps. A semiconductor structure having an upper exposed metal layer is provided. An ARC layer is formed over the upper exposed metal layer. The ARC layer having an upper surface. A first photoresist layer is formed upon the ARC layer. The first photoresist layer is removed by a rework process. The ARC layer upper surface is roughened to form a roughened ARC layer upper surface. A second photoresist layer is formed upon the roughened ARC layer upper surface whereby adhesion of the second photoresist layer to the ARC layer is improved.

Abstract: A method for plasma etching a wafer after a backside grinding process which incorporates an oxidation pretreatment step is disclosed. The method includes the step of first grinding a backside of a wafer to expose a bare silicon surface. The bare silicon surface is then oxidized in an oxidation chamber to form a substantially uniform silicon oxide layer of at least 50 Å thick, and preferably at least 100 Å thick. The wafer is then positioned in a plasma etch chamber with an active surface of the wafer exposed, and a surface layer etched away by an oxygen plasma without causing any further silicon oxide formation on the backside of the wafer. The present invention novel plasma etching method can be advantageously used for removing an organic material layer, such as a photoresist layer from a wafer surface.

Abstract: Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer.

Abstract: A method for avoiding oxide peeling by removing polymer contaminants from the edge of a wafer is described. An interlevel dielectric sandwich layer is formed by depositing a first oxide layer overlying semiconductor device structures in and on a semiconductor substrate, coating a spin-on-glass layer overlying the first oxide layer and rinsing the spin-on-glass layer whereby an edge bead rinse hump is formed a first distance from the edge of the wafer, etching back the spin-on-glass layer wherein the wafer is held by a clamp a second distance from the edge of the wafer wherein the second distance is smaller than the first distance and wherein the etching back of the spin-on-glass layer forms the polymer on the surface of the first oxide layer under the clamp at a third distance between the first and second distances, and depositing a second oxide layer overlying the etched back spin-on-glass layer and the polymer at the edge of the wafer to complete the interlevel dielectric sandwich layer.