Abstract: A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.

Abstract: A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

Abstract: A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

Abstract: A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.

Abstract: A method of forming a dual damascene structure. A substrate has a conductive line thereon. A first dielectric layer, a second dielectric layer, a base anti-reflection coating and a spin-on dielectric layer are sequentially formed over the substrate. The spin-on dielectric layer, the base anti-reflection coating and the second dielectric layer are patterned to form an opening in the second dielectric layer and a first trench in the spin-on dielectric layer and the base anti-reflection coating. Using the spin-on dielectric layer and the base anti-reflection coating as a mask, the exposed first dielectric layer within the opening is removed to form a via opening that exposes a portion of the substrate. The exposed second dielectric layer within the first trench is also removed to form a second trench that exposes a portion of the first dielectric layer. Thereafter, the spin-on dielectric layer and the base anti-reflection coating are removed.

Abstract: A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.