Abstract: Disclosed is a flash memory device and a program verification method thereof which can prevent a misjudgment as to whether flash memory cells are programmed or not. The flash memory device includes: a program verification voltage generator for variably generating program verification voltages used to verify whether the flash memory cells are programmed or not and a word line level selector for transferring the program verification voltages to word lines connected to control gates of the flash memory cells. The flash memory cells that are verified as uncertain as to whether the flash memory cells are programmed or not can be completely programmed since the program verification operation is carried out with program verification voltage levels that are changed according to the selective activations of the program verification control signals.

Abstract: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control. circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages.

Abstract: A non-volatile semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of bitlines and wordlines, each memory cell being programmed to one of plurality of data storage states. A node is connected to a selected bitline responsive to a storage state in a selected memory cell. A plurality of latched registers is connected to the node to store and output data bits corresponding the storage state, the data bits being assigned to the selected bitline. A circuit is adapted to precharge the selected bitline before sensing the selected memory cell and is adapted to equalize the selected bitline and the node after sensing the selected memory cell.