Abstract: An asynchronous transfer mode (ATM) host adapting apparatus comprising: a storage block for storing packet information, received cells, and parameters; an ATM network interface handling block for performing direct memory access of ATM cells and parameter stored therein, segmenting transmit packet information, reassembling received cells, transmitting and receiving the ATM cells to physical media cell received, and arbitrating in the direct memory access; and a secondary interface block for connecting the storage block to the ATM network interface handling block.

Abstract: The present invention discloses a processing circuit for STM-based ATM (Asynchronous Transfer Mode) cell physical layer.In the present invention are disclosed a general circuit structure having a multiplex, demultiplex unit between a byte processing unit and a parallel processing unit, a real-time transform method between 16 bit UTOPIA format and a standard ATM cell format in a ATM cell processing unit, and a control circuit which is normally in 9.times.270 mode and drives all the circuit in 9.times.30 mode in a special test mode.

Abstract: A received ATM layer OAM cell processing apparatus for processing in real time a fault management cell among ATM layer OAM cells of F4/F5 levels applied to a user network interface and a network node interface and performing CRC-10 and CRC-32 operations with respect to the other ATM layer OAM cells such as activation/deactivation cells, a resource management cell, a system management cell and a meta signaling cell, not processed in real time. Further, the received ATM layer OAM cell processing apparatus processes in real time a performance management cell among the ATM layer OAM cells of F4/F5 levels applied to the user network interface and network node interface.