Abstract: An electronic device is disclosed, including: a housing including a nonconductive area, a first printed circuit board (PCB) including a cavity and a fill-cut area, overlapping the nonconductive area, a first antenna module including at least one antenna array disposed in the cavity of the first PCB, a support frame coupled to one surface of the first PCB, supporting the first antenna module, a grip sensing pad surrounding the cavity and overlapping the fill-cut area, and a sensing circuit unit electrically connected to the grip sensing pad, configured to control an output power of the first antenna module based on inputs received via the grip sensing pad.

Abstract: Disclosed is a genome reconstruction method using whole genome data. According to the present invention, the genome reconstruction method reduces detection errors by converting a nucleotide sequence having a structural variation into a graph form, and then reconstructing the graph so that the structural variation and the copy number variation have consistent values. Thereafter, the genome arrangement form was restored by constructing a haplotype graph using heterozygous single nucleotide polymorphism information and then finding an Eulerian path with a minimum entropy value.

Abstract: A memory device includes a plurality of memory cells each programmed to have any one program state among a plurality of program states divided based on a threshold voltage thereof, and a peripheral circuit for performing a main program operation on the plurality of memory cells, and performing an additional program operation on at least one memory cell of which a threshold voltage regarding the main program operation is changed while the main program operation is being performed.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array, and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.

Abstract: There are provided a 3-D semiconductor device and a manufacturing method thereof. The 3-D semiconductor device includes a substrate extending along a first plane defined by first and second x and y directions, the substrate having a pipe transistor formed therein, a plurality of word lines spaced apart at regular intervals along a third direction z perpendicular to the first and second x and y directions; a first vertical plug connected to a first end of the pipe transistor by passing vertically through the word lines; a second vertical plug, connected to a second end of the pipe transistor by passing vertically through the word lines; a bit line connected to a top surface of the first vertical plug; and a source line connected to a top surface of the second vertical plug, wherein the first and second vertical plugs have different size.

Abstract: A semiconductor memory device may include a memory cell array including a plurality of memory cells, and a plurality of page buffers respectively coupled to a plurality of bit lines of the memory cell array, the page buffers being supplied with internal voltages to precharge the plurality of bit lines or to sense an amount of current flowing through the plurality of bit lines, during a sensing operation, wherein each of the page buffers converts the internal voltages into supply voltages having constant potential levels.

Abstract: A semiconductor memory device includes a memory cell array, and a voltage generator suitable for generating voltages supplied to the memory cell array. The memory cell array includes cell strings each including memory cells extending in a first direction and arranged in a second direction and a third direction; bit lines extending in the second direction and electrically coupled to the cell strings; and word lines extending in the third direction and electrically coupled to corresponding memory cells, wherein the word lines includes dummy word lines. A program voltage is supplied to a program word line that is electrically coupled to a memory cell to be programmed, and a level of a first dummy word line voltage supplied to a parallel dummy word line, which is disposed parallel to the program word line in the first direction is different from a level of a second dummy voltage supplied to a nonparallel dummy word line other than the parallel dummy word line.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array, and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.

Abstract: There are provided a storage device and an operating method thereof. A storage device includes a string including a plurality of memory cells, peripheral circuits for, in a read operation of a selected memory cell, applying a read voltage to a selected word line electrically coupled to the selected memory cell, and selectively applying a first pass voltage and a second pass voltage higher than the first pass voltage to unselected word lines electrically coupled to the other unselected memory cells according to a position of the selected word line, and a controller for controlling the peripheral circuits.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array; and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.

Abstract: There are provided a 3-D semiconductor device and a manufacturing method thereof. The 3-D semiconductor device includes a substrate extending along a first plane defined by first and second x and y directions, the substrate having a pipe transistor formed therein, a plurality of word lines spaced apart at regular intervals along a third direction z perpendicular to the first and second x and y directions; a first vertical plug connected to a first end of the pipe transistor by passing vertically through the word lines; a second vertical plug, connected to a second end of the pipe transistor by passing vertically through the word lines; a bit line connected to a top surface of the first vertical plug; and a source line connected to a top surface of the second vertical plug, wherein the first and second vertical plugs have different size.

Abstract: A semiconductor memory device includes a plurality of memory cells and an X-decoder. The plurality of memory cells are connected to a word line. The X-decoder is connected to the word line, and applies an operating voltage to the word line. In the semiconductor memory device, tunnel insulating layers included in the plurality of memory cells have different thicknesses according to distances of the plurality of memory cells from the X-decoder.

Abstract: A memory device includes a plurality of memory cells each programmed to have any one program state among a plurality of program states divided based on a threshold voltage thereof, and a peripheral circuit for performing a main program operation on the plurality of memory cells, and performing an additional program operation on at least one memory cell of which a threshold voltage regarding the main program operation is changed while the main program operation is being performed.

Abstract: A semiconductor memory device may include a memory cell array including a plurality of memory cells, and a plurality of page buffers respectively coupled to a plurality of bit lines of the memory cell array, the page buffers being supplied with internal voltages to precharge the plurality of bit lines or to sense an amount of current flowing through the plurality of bit lines, during a sensing operation, wherein each of the page buffers converts the internal voltages into supply voltages having constant potential levels.

Abstract: There are provided a storage device and an operating method thereof. A storage device includes a string including a plurality of memory cells, peripheral circuits for, in a read operation of a selected memory cell, applying a read voltage to a selected word line electrically coupled to the selected memory cell, and selectively applying a first pass voltage and a second pass voltage higher than the first pass voltage to unselected word lines electrically coupled to the other unselected memory cells according to a position of the selected word line, and a controller for controlling the peripheral circuits.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array; and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.

Abstract: Disclosed are a semiconductor device and an operating method thereof. The semiconductor device includes a plurality of memory blocks including cell strings coupled between bit lines and a source line, a peripheral circuit configured to perform an erase operation on a selected memory block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit, so that when an erase command is received, local word lines coupled to a non-selected memory block among the plurality of memory blocks are pulled to ground, the local word lines coupled to the non-selected memory block float after a pre-erase voltage lower than an erase voltage is applied to the source line, and the erase operation of the selected memory block is performed by applying the erase voltage to the source line.

Abstract: Disclosed are a semiconductor device and an operating method thereof. The semiconductor device includes a plurality of memory blocks including cell strings coupled between bit lines and a source line, a peripheral circuit configured to perform an erase operation on a selected memory block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit, so that when an erase command is received, local word lines coupled to a non-selected memory block among the plurality of memory blocks are pulled to ground, the local word lines coupled to the non-selected memory block float after a pre-erase voltage lower than an erase voltage is applied to the source line, and the erase operation of the selected memory block is performed by applying the erase voltage to the source line.

Abstract: A semiconductor apparatus includes a voltage supply circuit suitable for outputting a high voltage, a transfer circuit coupled between the voltage supply circuit and a peripheral circuit and suitable for transferring the high voltage to the peripheral circuit and a transfer control circuit suitable for outputting a transfer control signal to the transfer circuit to control the transfer of the high voltage to the peripheral circuit, wherein the transfer control circuit outputs the transfer control signal having a first positive voltage level to a gate of a transistor included in the transfer circuit when the voltage supply circuit outputs the high voltage to the transfer circuit.

Abstract: A semiconductor memory device includes a plurality of memory cells and an X-decoder. The plurality of memory cells are connected to a word line. The X-decoder is connected to the word line, and applies an operating voltage to the word line. In the semiconductor memory device, tunnel insulating layers included in the plurality of memory cells have different thicknesses according to distances of the plurality of memory cells from the X-decoder.