Patents by Inventor Yeong-Shin PARK

Yeong-Shin PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963440
    Abstract: A compound of Chemical Formula 1, and an organic photoelectric device, an image sensor, and an electronic device including the same are disclosed: In Chemical Formula 1, the definition of each group and parameter is as described in the detailed description.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taejin Choi, Jeong Il Park, Jisoo Shin, Sung Young Yun, Seon-Jeong Lim, Youn Hee Lim, Yeong Suk Choi, Hye Rim Hong
  • Patent number: 10580688
    Abstract: Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chul Yoon, Yeong-Shin Park, Joonghee Kim, Jihee Kim, Dongjun Shin, Kukhan Yoon, Taeseop Choi, Jungheun Hwang
  • Patent number: 10410919
    Abstract: A method of fabricating a wiring structure for a semiconductor device may include forming a lower wiring in a lower insulating layer, forming an etch stop layer covering the lower insulating layer and the lower wiring, forming an interlayer insulating layer on the etch stop layer, forming a preliminary via-hole through the interlayer insulating layer, partially etching the interlayer insulating layer to form a trench partially merged with the preliminary via-hole and a via-hole defined by a remaining portion of the preliminary via-hole, removing the etch stop layer exposed by the via-hole to expose the lower wiring, partially etching a contact area at which the trench and the via-hole are in contact with each other and forming an upper wiring in the via-hole and the trench to be electrically connected to the lower wiring.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeong-Shin Park, Young-Jae Kim
  • Publication number: 20190214295
    Abstract: Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.
    Type: Application
    Filed: July 17, 2018
    Publication date: July 11, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chul YOON, Yeong-Shin Park, Joonghee Kim, Jihee Kim, Dongjun Shin, Kukhan Yoon, Taeseop Choi, Jungheun Hwang
  • Publication number: 20170236751
    Abstract: A method of fabricating a wiring structure for a semiconductor device may include forming a lower wiring in a lower insulating layer, forming an etch stop layer covering the lower insulating layer and the lower wiring, forming an interlayer insulating layer on the etch stop layer, forming a preliminary via-hole through the interlayer insulating layer, partially etching the interlayer insulating layer to form a trench partially merged with the preliminary via-hole and a via-hole defined by a remaining portion of the preliminary via-hole, removing the etch stop layer exposed by the via-hole to expose the lower wiring, partially etching a contact area at which the trench and the via-hole are in contact with each other and forming an upper wiring in the via-hole and the trench to be electrically connected to the lower wiring.
    Type: Application
    Filed: October 18, 2016
    Publication date: August 17, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Shin PARK, Young-Jae KIM