Abstract: A display driver circuit includes a comparator that is configured to compare first pixel data of a plurality of pixel data with second pixel data of the plurality of pixel data, the plurality of pixel data respectively corresponding to a plurality of pixels connected to a data line, a pre-emphasis controller configured to calculate an offset based on a compare result of the comparator and gamma segment points, which are adjacent to the second pixel data, from among a plurality of gamma segment points used as a reference for dividing the plurality of pixel data, a calculator configured to calculate pre-emphasis pixel data based on the second pixel data and the offset, and an output circuit configured to transmit a pre-emphasis gray scale voltage corresponding to the pre-emphasis pixel data and a target gray scale voltage corresponding to the second pixel data to a display panel through the data line.

Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.

Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.