Patents by Inventor Yeou-Lang Hsieh
Yeou-Lang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7750470Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.Type: GrantFiled: February 8, 2007Date of Patent: July 6, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yeou-Lang Hsieh, Chin-Min Lin, Jiann-Jong Wang
-
Publication number: 20080191249Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Inventors: Yeou-Lang Hsieh, Chin-Min Lin, Jiann-Jong Wang
-
Patent number: 7362603Abstract: A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area. One edge of the first memory cell area shifts away from its corresponding edge of the second memory cell area. Thus, the area or yield rate of the memory device can be adjusted.Type: GrantFiled: May 25, 2006Date of Patent: April 22, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yeou-Lang Hsieh, Ching-Kun Huang, Jeng-Dong Sheu
-
Patent number: 7348654Abstract: RF devices formed in integrated circuit devices include a top metal level overlying a substrate. The top metal level comprises pads and portions of planned RF devices and an RF metal level overlying the top metal level completes the RF devices which may be an interconnected RF network that may include capacitors, inductors or both. Openings are formed in a passivation layer overlying the RF metal level to provide direct access to the RF devices. The interconnected RF network may include fuses enabling the network to be selectively altered by cutting relatively thin interconnect lines using a laser directed through the openings. The RF devices or portions of the RF network may be directly coupled to external devices and utilized in SOC (System On a Chip) and SIT (System In Package) technologies.Type: GrantFiled: April 14, 2005Date of Patent: March 25, 2008Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yeou-Lang Hsieh, Ching-Kwun Huang, Yi-Jing Chu
-
Publication number: 20070272985Abstract: A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area. One edge of the first memory cell area shifts away from its corresponding edge of the second memory cell area. Thus, the area or yield rate of the memory device can be adjusted.Type: ApplicationFiled: May 25, 2006Publication date: November 29, 2007Inventors: Yeou-Lang Hsieh, Ching-Kun Huang, Jeng-Dong Sheu
-
Patent number: 7196012Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.Type: GrantFiled: March 16, 2005Date of Patent: March 27, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yeou-Lang Hsieh, Chin-Min Lin, Jiann-Jong Wang
-
Patent number: 7183625Abstract: A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.Type: GrantFiled: August 26, 2004Date of Patent: February 27, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Yeou-Lang Hsieh
-
Publication number: 20050227490Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.Type: ApplicationFiled: March 16, 2005Publication date: October 13, 2005Inventors: Yeou-Lang Hsieh, Chin-Min Lin, Jiann-Jong Wang
-
Publication number: 20050194350Abstract: RF devices formed in integrated circuit devices include a top metal level overlying a substrate. The top metal level comprises pads and portions of planned RF devices and an RF metal level overlying the top metal level completes the RF devices which may be an interconnected RF network that may include capacitors, inductors or both. Openings are formed in a passivation layer overlying the RF metal level to provide direct access to the RF devices. The interconnected RF network may include fuses enabling the network to be selectively altered by cutting relatively thin interconnect lines using a laser directed through the openings. The RF devices or portions of the RF network may be directly coupled to external devices and utilized in SOC (System On a Chip) and SIT (System In Package) technologies.Type: ApplicationFiled: April 14, 2005Publication date: September 8, 2005Inventors: Yeou-Lang Hsieh, Ching-Kwun Huang, Yi-Jing Chu
-
Publication number: 20050077592Abstract: A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.Type: ApplicationFiled: August 26, 2004Publication date: April 14, 2005Inventor: Yeou-Lang Hsieh
-
Patent number: 6800534Abstract: A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.Type: GrantFiled: December 9, 2002Date of Patent: October 5, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Yeou-Lang Hsieh
-
Publication number: 20040110355Abstract: A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.Type: ApplicationFiled: December 9, 2002Publication date: June 10, 2004Applicant: Taiwan Semiconductor Manufacturing CompanyInventor: Yeou-Lang Hsieh
-
Patent number: 6236096Abstract: A structure and producing method of a three-electrode capacitive pressure sensor can integrate and produce sensor capacitor and reference capacitor in the same pressure sensor cavity. This dual capacitor integration structure can cancel off environment interference of the same mode by differentiated circuit. Avoiding connection between upper and lower electrode plates can be achieved through the existence of a third electrode plate. In working pressure interval from 25 psi to 40 psi, the sensitivity of said three-electrode capacitive sensor is a 0.21 pF/psi, while the sensitivity of an ordinary planar connection pressure sensor is 0.05 pF/psi. The merits of said three-electrode capacitive pressure sensor include trivial production procedure and connection with planar and high sensitivity.Type: GrantFiled: September 12, 2000Date of Patent: May 22, 2001Assignee: National Science Council of Republic of ChinaInventors: Kow-Ming Chang, Gwo-Jen Hwang, Yeou-Lang Hsieh