Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract: A chemical vapor deposition (CVD) method for forming a microelectronic layer within a microelectronic product employs a wetting material treatment of a substrate upon which is formed the microelectronic layer. The wetting material treatment provides for an attenuated incubation or induction time when forming the microelectronic layer, particularly within the context of a digital CVD method, such as an atomic layer CVD method. The microelectronic layer is thus formed with enhanced manufacturability.

Abstract: A new Inter Poly Dielectric (IPD) layer is provided for use in creating ultra-small gate electrodes. A first and a second high-k dielectric film are provided which remain amorphous at relatively high processing temperatures. The first high-k dielectric film is of Al3O5—ZrO2—Al3O5, the second high-k dielectric film is aluminum doped ZrO2 or HfO2.

Abstract: A new Inter Poly Dielectric (IPD) layer is provided for use in creating ultra-small gate electrodes. A first and a second high-k dielectric film are provided which remain amorphous at relatively high processing temperatures. The first high-k dielectric film is of Al3O5—ZrO2—Al3O5, the second high-k dielectric film is aluminum doped ZrO2 or HfO2.

Abstract: A low temperature ozone-enhanced oxidation process is presented whereby amorphous high dielectric constant film devices are subject to oxidation processes at temperatures whereby crystallization of the amorphous high dielectric constant film is avoided, thereby lowering leakage currents and reducing the required thickness to achieve an equivalent SiO2 thickness (EOT)

Abstract: A low temperature ozone-enhanced oxidation process is presented whereby amorphous high dielectric constant film devices are subject to oxidation processes at temperatures whereby crystallization of the amorphous high dielectric constant film is avoided, thereby lowering leakage currents and reducing the required thickness to achieve an equivalent SiO2 thickness (EOT).