Patents by Inventor Yeoung-Jun Cho

Yeoung-Jun Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204892
    Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
  • Patent number: 9847319
    Abstract: A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: December 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Sub Song, Sung-Wook Hwang, Yeoung-Jun Cho, Ki-Hong Jeong, Tae-Heum Kim
  • Publication number: 20170358564
    Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 14, 2017
    Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
  • Publication number: 20170025385
    Abstract: A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages.
    Type: Application
    Filed: May 6, 2016
    Publication date: January 26, 2017
    Inventors: SANG-SUB SONG, SUNG-WOOK HWANG, YEOUNG-JUN CHO, KI-HONG JEONG, TAE-HEUM KIM
  • Patent number: 8692133
    Abstract: Provided is a semiconductor package. The semiconductor package includes an insulation substrate with top and bottom surfaces. The semiconductor package further includes a circuit pattern on the top surface. The circuit pattern includes a first signal conductive pattern and first and second ground conductive patterns. The semiconductor package includes a first insulation film covering the first signal conductive pattern and exposing a first portion of the first ground conductive pattern and a portion of the second ground conductive pattern. The semiconductor package further includes a first conductive member on the first signal conductive pattern and the first and second ground conductive patterns. The first conductive member electrically connects the first and second ground conductive patterns by covering a portion of the first insulation film and coming in contact with the first portion of the first ground conductive pattern and the portion of the second ground conductive pattern.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yeoung-Jun Cho
  • Publication number: 20100238638
    Abstract: Provided is a semiconductor package. The semiconductor package includes an insulation substrate with top and bottom surfaces. The semiconductor package further includes a circuit pattern on the top surface. The circuit pattern includes a first signal conductive pattern and first and second ground conductive patterns. The semiconductor package includes a first insulation film covering the first signal conductive pattern and exposing a first portion of the first ground conductive pattern and a portion of the second ground conductive pattern. The semiconductor package further includes a first conductive member on the first signal conductive pattern and the first and second ground conductive patterns. The first conductive member electrically connects the first and second ground conductive patterns by covering a portion of the first insulation film and coming in contact with the first portion of the first ground conductive pattern and the portion of the second ground conductive pattern.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 23, 2010
    Inventor: Yeoung-Jun Cho
  • Patent number: 7566961
    Abstract: A multi-stacked package includes a first package, a second package and a combining member. The second package supports the first package, and is electrically connected to the first package and has at least one joint hole. The combining member extends from the first package to below the second package to pass through the joint hole so that the combining member is partially exposed to improve the coherence between the first package and the second package.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: July 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yeoung-Jun Cho
  • Publication number: 20070138631
    Abstract: A multi-stacked package includes a first package, a second package and a combining member. The second package supports the first package, and is electrically connected to the first package and has at least one joint hole. The combining member extends from the first package to below the second package to pass through the joint hole so that the combining member is partially exposed to improve the coherence between the first package and the second package.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 21, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yeoung-Jun CHO