Abstract: A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.

Abstract: A host controller transfers data over a bus communication system, under the control of a processor, in individual transactions. A processor interrupt request is generated on completion of a transaction. The host controller comprises logic such that, when a processor interrupt request is generated on completion of a transaction from a first group of the individual transactions, an interrupt request is sent to the processor, whereas when a processor interrupt request is generated on completion of a transaction from a second group of the individual transactions, an interrupt request is not sent to the processor. Further, when a processor interrupt request is generated on completion of a transaction from a third group of the individual transactions, an interrupt request is sent to the processor only when interrupt requests are generated on completion of transactions.

Abstract: A host controller can be used in transferring data over a USB bus communication system in frames and micro-frames. Each data transfer is described by a packet transfer descriptor, and a packet transfer descriptor for a data transfer includes a bit map, such that data is transferred according to the packet transfer descriptor only during those micro-frames of a frame which correspond to bits of the bit map for which the bit value has been set to an active value.

Abstract: An electronic device, operating as a USB host, has an embedded processor and a system memory, connected by a memory bus. A host controller integrated circuit does not need to master the system memory, but instead acts purely as a slave. The embedded processor is then adapted to write the data to the host controller integrated circuit in the form of transfer-based transactions.

Abstract: A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.

Abstract: A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.